A Novel Space Vector Technique for the Direct Three-level Matrix Converter

This study proposes a novel Direct Torque Control (DTC) method for the Direct Three level Matrix Converter (DTMC), which uses both the input phase voltage vectors (short vectors) and the input line voltage vectors (long vectors). The problem of voltage imbalance at the input filter capacitance due to the use of the short vectors is addressed with an additional voltage hysteresis comparator. With the errors of torque, flux, sin Ψ and the neutral point voltage, an Optimum Switching Table (OST) is designed for the DTMC. The OST generates the necessary switching signals for the DTC of the DTMC. The DTMC topology with the modified ISVM technique reduces the THD at the output. The proposed DTMC Indirect Space Vector pulse width Modulation (ISVM) technique uses the idea of multilevel inverter SVM technique along with the proposed neutral current balancing strategy for generating the firing pulses. The switching loss model for the DTMC is developed and the performance of the DTMC is compared with that of the Conventional Matrix Converter (CMC). The performance of the proposed DTC technique for the DTMC is evaluated through simulation to explain the reduced torque ripple characteristics. To validate the proposed DTMC ISVM technique, a 3 kVA direct multilevel matrix converter prototype was developed.


INTRODUCTION
The Matrix Converter is an attractive topology of power converter for variable speed AC drive applications, which converts the AC to AC in a single stage.The advantages of the matrix converter are its capability of producing a variable output voltage with unrestricted input and output frequency, the absence of electrolytic capacitors and the potential to increase the power density, reduced size, reduced weight and better input power quality.However, industrial applications of these converters are limited because of some practical issues such as complex control strategies, high susceptibility to input power disturbances, common mode voltage effects and low voltage transfer ratio.Recently, matrix converters have experienced a resurgence of attention due to the advancements in the semiconductor device industry and the growth of processor technologies, which promises practical implementation of matrix converters in the control of drives.The matrix converter is the force-commutated version of the cyclo-converters (Huber and Borojevic, 1989), which overcomes the disadvantage of the conventional cyclo-converter such as the limitations in the frequency conversion, rich output voltage harmonics and increased number of switches (Rashid, 2005;Fa-Hai et al., 1994).The indirect or the sparse matrix converter is a cascade of the controlled rectifier and inverter topologies without a DC link in between (Boost and Ziogas, 1988).
The voltage stresses on the power devices can be reduced by using Multi-Level Inverters (MLIs) (Celanovic and Boroyevich, 2000;Lopez et al., 2008;Aneesh et al., 2009).MLIs permit the use of lower rating power supplies and power devices for achieving higher output power rating.Using the same idea in the matrix converters, a new family of converters called multilevel matrix converters evolved with different concepts: i) Replacing each bidirectional switch in the CMC with n cells, each cell consisting of a capacitor connected to the centre of the H Bridge (Erickson and Al-Naseem, 2001;Erickson et al., 2006).This topology generates multi-level output but at the cost of a more complicated circuit configuration and modulation strategy.ii) Modifying the topology of the IMC with additional switches, which makes available two different voltages levels at the output, i.e., the phase and the line voltages (Meng et al., 2010).This topology is effective for two-level and three-level voltage conversion with less complicated circuit configuration and modulation strategy as compared to (i).Modified IMC based three-level converter uses the diode clamped multi-level space vector technique (Meng et al., 2010) on the inverter side and the conventional space vector technique on the rectifier side.The main objective of this study is to develop a new class of Direct Three-level Matrix Converter (DTMC) along with its modulation techniques and to analyze its performance with the existing techniques.

Problem formulation:
The objective of this study is to develop a new DTMC topology namely, the direct three-level matrix converter, which requires three bidirectional switches of lower ratings (phase voltage rated) and the CMC topology.The structure is a 4×3 matrix converter that facilitates the increase in the output voltage levels by making the source neutral available to the load terminals.In addition to the multilevel operation, the converter also has the ability to control bi-directional power flow.The proposed DTMC is evaluated by simulation and hardware experimentation.The modulation strategy of the DTMC uses the multi-level space vector modulation technique along with the proposed neutral current balancing strategy.The same is implemented using the Xilinx based system generator facility, which is available as a toolbox in MATLAB R2010a, along with an FPGA.

Methodology:
A DTMC in its very generic form, shown in Fig. 1, consists of three arms that are connected to the source and one arm connected to the star point (neutral) of the input filter capacitances.Figure 1 depicts the general configuration of the proposed DTMC structure which consists of a CMC and a neutral point connecter.

Indirect matrix converter representation for the DTMC:
The proposed DTMC topology consists of an array of 4×3 bi-directional switches, which includes the 3×3 switches of the CMC and three additional switches for making the neutral point of the input filter capacitance to be available at the load terminals.Equation ( 1) and ( 2) give the output voltages and the input currents of the DTMC: Since the DTMC is supplied by a voltage source, the input phases must never be shorted and due to the inductive nature of the load, the output phases must never be left open.These constraints are realized by Eq. ( 3 and a Fictitious Inverter (FI-output converter), as shown in Fig. 2. The FTC consists of three phase arms and one neutral arm.Switching ON any of the two phase arms leads to the line voltage being available at the FDCB and switching ON any one phase arm with the neutral arm leads to the phase voltage being available at the FDCB.This results in twelve active voltage vectors on the rectifier side.This decoupled representation simplifies the control of the input current and the output voltage in DTMC, as described in the next section.

Space vector modulation technique for the DTMC:
The switching function for the DTMC is represented as the product of the rectifier switching function and the inverter switching function and is given by Eq. ( 4 The switching states for synthesizing the required currents and voltages are described in the following subsections. The fictitious two-level converter stage: Assuming that the output of the FTC is a constant current source I DC , the space vector for all valid switching states are determined by Eq. ( 5) to ( 7 As described earlier, switching ON the neutral arm causes the current to flow in the source neutral resulting in the space vector having a component along the I 0 axis.Table 1 gives the space vector components for different valid switching states and Fig. 3a shows the space vectors distribution: Vectors represented by I Li (active long vectors) are conventional rectifier space vectors, which do not contribute to the neutral current.Vectors represented by I Pi (active short vectors) contribute to the neutral current.To ensure that the input current is sinusoidal, the reference space vector must lie on the αβ plane requiring the neutral current to be zero on application of the vector I Pi .This is carried out by applying equally the adjacent I Pi vectors, which lie on the upper and the lower halves of the αβ plane.This ensures that the average neutral current is zero over a switching period.The example in Table 2 explains the same.
This solution to the neutral current balancing problem (Celanovic and Boroyevich, 2000) introduces virtual vectors I VPi , which lie completely on the αβ plane, as given in Table 3 and shown in Fig. 3b.
shows the sector zero of the space vector diagram of the FTC.Each sector consists of two active long vectors, two active virtual short vectors and four zero vectors.To synthesize the required reference input current and the FDCB voltage, the three nearest current vectors (Busquets-Monge et al., 2004) are selected, as shown in Fig. 4b, depending on the modulation index m c of the FTC.
In order to identify the region in which the reference vector lies, equations of the three lines are derived and shown in Fig. 5. Table 4 gives the rules for identifying the region in which the reference vector lies in the FTC for different values of modulation indices m c .
Duty cycles of the selected vectors for different regions are computed using Eq. ( 8), where (x i , y i ) are the coordinates of the selected vector I i and d i is its duty cycle.X and Y are the coordinates of the reference vector I REF and are given by Eq. ( 9): While computing the duty cycle, the sector in Fig. 6a is rotated as shown in Fig. 6b.The coordinates are chosen according to the region in which the reference vector lies, as shown in Fig. 6b.Table 5 gives the duty cycles derived for different regions.where, m DTMC is the required modulation index of the DTMC.At higher modulation indices, the FTC reference vector, I in , lies in any one of the regions R 1 , R 2 , R 3 or R 4 .These regions do not use any zero vectors for the modulation.Simultaneous use of the zero vectors at the inverter stage would cause the output voltage to become zero.This is not consistent with the idea of multilevel switching techniques as it increases the THD at the output.To decrease the THD of the DTMC, zero vectors are not used at the inverter stage, which does not allow for the change in modulation index m v .With the elimination of the zero vectors, the duty cycles for active vectors are recomputed as given in Eq. ( 12).This increases the output voltage vector as given by Eq. ( 13).Thus the reference vector is brought outside the inscribed circle of the space vector hexagon leading to an over modulation condition: The increase in the output voltage vector is compensated by adjusting the FDCB voltage by modifying the modulation index of the FTC dynamically, as given by Eq. ( 14): Figure 8 shows the allocation of the switching vectors in a sampling period for a particular inverter sector and for different regions of the converter sector.The period of the virtual vector is divided into two, during which the adjacent upper and lower active short vectors of the corresponding virtual vector is applied.The real-time switching pattern for the DTMC is computed for each vector combination of the FTC and the FI using Eq.(4). Figure 8a shows the switching pattern for the DTMC for regions R 1 and R 2 when only one active virtual vector is used.Figure 8b shows the switching pattern for the DTMC for regions R 3 , R 4 and R 5 when two active virtual vectors are used.

DTMC operation under abnormal input conditions:
From Eq. ( 14) it can be shown that within a sector, m c reaches the peak once when (d γ + d δ ) = 1 and reaches the minimum value twice when (d γ = 0) or (d δ = 0) and this repeats for all the six sectors.Hence the dynamic variation of the m c introduces a sixth harmonic  9a, where f i is the fundamental frequency of the input voltage.
It was shown in chapter 4 that an input unbalance introduces a second harmonic component 2f i at the FDCB of the CMC.Hence, the FDCB voltage of DTMC, as shown in Fig. 9b, contains two components 6f i and 2f i during the input unbalance.
The instantaneous variation can be determined by Eq. ( 15), where V R , V S and V T are the FDCB voltage on applying the switching vectors I 1 , I 2 and I 3 , respectively: To mitigate the effects of the unbalance at the output, as explained in chapter 4, the input voltage of the FI must be limited to the minimum of the FDCB voltage V DC over an input cycle expressed as V DC_Min .This is achieved by dynamically modifying m c , as given in Eq. ( 16).This mitigates the effect of unbalance and harmonics in the output currents while the input current harmonics are left uncompensated:

MODELING OF LOSSES IN THE CMC AND THE DTMC
There are three types of losses in power semiconductor devices namely the ON, the OFF and the switching losses.The power loss in the device when it is "OFF" is negligible compared to its power loss when it is either "ON" or when it is undergoing transition.The power loss in the device during its 'ON' state is called the conduction loss while the power losses in the device during its transition ('ON' to 'OFF' or viceversa) states is called the switching loss.Conduction loss is the product of the voltage drop across the device and the current through the device, when it is in the 'ON' state.Switching loss is proportional to the product of blocking voltage and conduction current at the instant of switching; and if this is significant, it is termed as hard switching loss (Bierhoff and Fuchs, 2004).If the switching occurs when either the current through the device or the voltage across the device is nearly zero, the commutation is referred to as 'soft switching' and the switching loss in the device is negligible.For an IGBT, there are two types of losses during hard switching: T on_losses and T off_losses , associated with the device turn-ON and turn-OFF process, respectively.For a diode, the switching loss is caused by reverse recovery mechanism that occurs only during the diode turn-OFF.Hence, the turn-ON loss for a diode is not considered.
Conduction loss modeling for the CMC and the DTMC: From Eq. (3), it can be seen that in each phase only one switch conducts at any given time.Hence, there is always only one IGBT that conducts and only one diode that conducts at an output phase of the CMC and the DTMC.Equation ( 17) and (18) give the conduction loss and the conduction energy of one output phase in each switching cycle: given by Eq. ( 19) and ( 20): where, x, y, z, m, n and k are constants that are obtained from the curve fitting equation of V ce -I c characteristics given in the datasheet of the device used.Then the average conduction loss over an interval T, for the CMC and the DTMC, is give by Eq. ( 21): Switching loss modeling for the CMC and the DTMC: During switching transients, the switching energy is described by Eq. ( 22) (Wang and Venkataramanan, 2006;Apap et al., 2003): where, V R , i R and E swR are, respectively the voltage, current and switching energy of the device at the rated V R and i R .From the four step commutation procedure, it can be seen that when commutation happens between the bidirectional switch S 1 to switch S 2 under the condition of V in >0 and I out >0, commutation losses do not occur for switches S 1 -, S 2 + and S 2 -.This is because the switches S 1 -and S 2 -do not block any voltage and the switch S 2 + does not conduct current.This creates only a turn OFF loss for the switch S 1 + .Similarly, S 2 to S 1 transition creates a turn ON loss for the switch S 1 + and a turn OFF loss for the diode D 2 -.Table 6 summarizes the switching energy losses for commutation between S 1 and S 2 evaluated for all conditions of input voltages and output currents.
From Table 6, it can be generalized that two commutation events, i.e.: • First phase to second phase transition and • Second phase to first phase transition within a switching cycle produces three switching losses namely  OFF switching energy at the rated V R and i R .In general, for a particular transition from the input phase x to the input phase y and vice-versa the switching loss is given by Eq. ( 23): From the T delay -I c characteristics of the datasheet, T on , T off and T r are identified.Equation ( 24) gives the switching power loss: Switching energy calculation for the CMC: Switching losses depend on the modulation technique.
In this study, a double-sided space vector switching technique is selected for the CMC as well as the DTMC.It can be seen that the optimized switching technique (Nielsen et al., 1996) leads to eight commutation events over all the three output phases in a switching cycle T s .Four of these commutation events occur in an output phase and two commutation events each occur in the other two output phases.From Fig. 10, it can be seen that the total switching energy of the CMC over a sampling time T s is given by Eq. ( 25):   where, K = (E on + E off + E rr_D ) / (V R ×i R ).For other voltage and current sectors, Eq. ( 25) can be generalized as Eq. ( 26): Switching energy calculation for the DTMC: In the DTMC, two types of commutation events occur namely: • The line commutation where the blocking voltage is the line voltage • The phase commutation where the blocking voltage is the phase voltage Extending the optimized indirect space vector switching's for the DTMC, the number of commutation events for a particular voltage sector X and different regions of current sector Y is calculated and given in Table 7. Equation ( 27) to (31) give the total switching energy of the DTMC over a sampling time T for the voltage sector 1 and different regions of the current sector 1.
Region 1: Region 2: Region 3: Region 4: Region 5: The switching and conduction losses for the DTMC were derived and compared with those for the CMC.A complete loss model was developed using the SIMULINK blockset in MATLAB.Through simulations, switching energy losses for different regions for different sectors of the current and the voltage are calculated using the above procedure and results obtained are discussed and presented in the next section.

RESULTS AND DISCUSSION
To evaluate the performance of the proposed topology with the modified space vector technique, simulation with R-L load was performed.Table 8 gives the simulation parameters.
For modulation indices between 3/4 and 3/2, the output voltage switches between the active long vectors and the active short vectors but for lower modulation indices, the output voltage switches between the active short vectors and the zero vectors.Figure 11 shows the output phase voltages, output line voltages, input currents and output currents for the voltage transfer ratio that is changed from 0.72 to 0.5 at 0.4 sec and 0.5 to 0.25 at 0.5 sec.The harmonic content of the input and the output currents increase with decrease in the voltage transfer ratio.In the CMC, the peak of the output voltage is 3 times the input voltage for all values of modulation indices.However, in the DTMC, the peak of the output voltage is 3 times the input voltage for the modulation indices greater than 3/4 while the peak of the output voltage is 3/2 times the input voltage for modulation indices lesser than 3/4.This leads to lower switching stress on the power devices in the case of the DTMC.
A 20% unbalance in the phase B was introduced.In addition, second and third harmonics with magnitudes of 4 and 7% of the fundamental respectively were added to all the three phases as shown in Fig. 12a.By dynamically modifying the modulation index, as explained in the previous section, the effect of the unbalance and harmonics has been mitigated in the output voltages and currents, as shown in Fig. 12b and d.The unbalanced input currents are shown in Fig. 12c.At very low modulation index, the THD for the DTMC reduces by approximately 58% as compared to the CMC due to the use of phase Fig. 14a, it can be observed that the conduction losses are always greater than the switching losses in the CMC, for different values of MIs. Figure 14b shows that as the input power factor decreases, the output power of the converter also decreases.
The conduction losses for the DTMC and the CMC are the same under all operating conditions.However, the switching losses for the DTMC are higher than the At very low modulation index, the THD for the DTMC reduces by approximately 58% as compared to phase vectors.From Fig. 14a, it can be observed that the conduction losses are always greater than the switching losses in the CMC, for different values of MIs. Figure 14b shows that as the input power factor decreases, the output conduction losses for the DTMC and the CMC are the same under all operating conditions.However, or the DTMC are higher than the switching losses of the CMC for all MIs, since the switching events are more in the DTMC than in the CMC.With a double side banded SVM, the DTMC exhibits higher switching losses for all values of MIs.Nevertheless, for the single sided SWM, the DTMC exhibits higher switching losses for lower values of MIs and lower switching losses for higher values of MI This is because the switching events of the regions R R 4 and R 5 are very high compared to the switching events of the regions R 1 and R 2 , as shown in Fig. 15.
Hardware implementation: To validate the proposed switching algorithm, a 3 kVA direct converter prototype was developed.The setup consists of a control circuit, CONCEPT gate driver module (6SD106EI), multilevel matrix converter module with bidirectional switches (SEMIKRON control circuit consists of an FPG DSP-XC3S1800A) for generating switching pulses for the DTMC.switching losses of the CMC for all MIs, since the switching events are more in the DTMC than in the MC.With a double side banded SVM, the DTMC exhibits higher switching losses for all values of MIs.Nevertheless, for the single sided SWM, the DTMC exhibits higher switching losses for lower values of MIs and lower switching losses for higher values of MIs.This is because the switching events of the regions R 3 , are very high compared to the switching , as shown in Fig. 15.
To validate the proposed switching algorithm, a 3 kVA direct multilevel matrix converter prototype was developed.The setup consists of a control circuit, CONCEPT gate driver module (6SD106EI), multilevel matrix converter module with bidirectional switches (SEMIKRON-SK60GM123).The control circuit consists of an FPGA (SPARTEN 3A XC3S1800A) for generating switching pulses for The switching information and the current direction information were processed using the FPGA for generating the DTMC switching pulses along with the implementation of the four-step com system generator toolbox in the MATLAB was used to generate the FPGA code in VHDL for generating the firing pulses.The experiment was conducted with a balanced input phase voltage of 100 V, switching frequency of 6 kHz, R L = 20 Ω, L L MI = 0.72.The DTMC was used for converting the 50 Hz input voltage to 25 Hz output voltage.Figure 16 shows the laboratory prototype of the DTMC.Selected waveforms from experimental results shown in Fig. 17 verify the implementation and the effectiveness of the proposed DTMC ISVM method.Figure 17a and b show the output line voltage and the output phase voltage of the DTMC, respectively.Figure 17c shows the 25 Hz output current of the DTMC and Fig. 17d shows the 50 Hz filtered input current of the DTMC.

CONCLUSION
In this study, the space vector PWM technique for the direct three-level matrix converter has been The switching information and the current direction information were processed using the FPGA for generating the DTMC switching pulses along with the step commutation.The system generator toolbox in the MATLAB was used to generate the FPGA code in VHDL for generating the firing pulses.The experiment was conducted with a balanced input phase voltage of 100 V, switching L = 21 mH and 0.72.The DTMC was used for converting the 50 Hz input voltage to 25 Hz output voltage.Figure 16 shows the laboratory prototype of the DTMC.Selected waveforms from experimental results shown in Fig. 17 the effectiveness of the proposed DTMC ISVM method.Figure 17a and b show the output line voltage and the output phase voltage of the DTMC, respectively.Figure 17c shows the 25 Hz output current of the DTMC and Fig. 17d shows the 50 In this study, the space vector PWM technique for level matrix converter has been proposed for synthesizing balanced sinusoidal three level output voltages from balanced and unbalanced non-sinusoidal input voltages.In addition, conduction losses and switching losses were modelled for the DTMC and a comparative study of the same for the CMC and the DTMC has been carried out.MATLAB simulation and hardware results verify the effectiveness of the proposed technique.The THD of the output voltage is lower for the DTMC as compared to the CMC.However, the switching losses for the DTMC are higher than those of the CMC.
Fig. 1: Topology of the direct three-level matrix converter Fig. 3: (a) Space vectors of the FTC (b) space vectors and virtual vectors of the FTC Fig. 4: (a) Sector region identification of the FTC (b) region vector identification of the FTC

5 •
Fig. 6: (a) Sector 1 and (b) sector 1 rotated Fig. 9: (a) Calculated FDCV with a balanced input voltage (b) calculated FDCB voltage with an unbalanced input voltage component 6f i at the FDCB, as shown in Fig.9a, where f i is the fundamental frequency of the input voltage.It was shown in chapter 4 that an input unbalance introduces a second harmonic component 2f i at the FDCB of the CMC.Hence, the FDCB voltage of DTMC, as shown in Fig.9b, contains two components 6f i and 2f i during the input unbalance.The instantaneous variation can be determined by Eq. (15), where V R , V S and V T are the FDCB voltage on applying the switching vectors I 1 , I 2 and I 3 , respectively: Fig. 10: Commutation events of the CMC in a switching period for voltage sector 1 and current sector 1 26) where, x, y and z take any of the values |v AB |, |v BC |, |v AC |, (|v AB | + |v BC |) or (|v AB | + |v AC |) depending on the sectors of the current and the voltage.

Fig. 11 :Fig. 13 :
Fig. 11: Performance of the DTMC with a balanced supply for different modulation indices (0.72, 0.5, 0.25) (a) output phase voltage, (b) output line voltage, (c) input phase current, (d) output phase current losses for the DTMC and the CMC for different values of MI modulation index, as in the case of the CMC, because of the use of the zero

Fig. 17 :
Fig. 17: Hardware output for balanced input condition (a) output phase voltage, (b) output line (d) input phase current balanced input condition (a) output phase voltage, (b) output line voltage, (c) output phase current

Table 1 :
Space vectors for the fictitious two-level converter

Table 2 :
Neutral current balancing and virtual vector synthesis Switching timeApplied vectors I

Table 5 :
Duty cycles for different regions in a given sector d IGBT {i L { : The ON state voltage drop in the IGBT v d DIODE {i L { : The ON state voltage drop in the diode and v

Table 6 :
Switching energy losses for switch S1 to switch S2 transition swR = E on + E off + E rr_D where, E on and E off are the switching energy for the IGBT ON and IGBT OFF switchings at the rated V R and i R .E rr_D is the DIODE

Table 7 :
Commutation events in a switching cycle Ts Converter sector -Y and inverter sector -X (regions of converter sector)

Table 8 :
Simulation parameters for the DTMC topology