Digital Decimation Filter of Adsl: Design and Implementation

In this study four proposed structures for the digital decimation filter which is used in D A / ∑ ∆ converters of Asymmetrical Digital Subscriber Line (ADSL) are presented. Single multi rate (Finite Impulse Response) FIR, single multi rate (Infinite Impulse Response) IIR, three stages comb-FIR-FIR and comb-IIR-FIR are the four proposed structures. The hardware minimization is considered for each structure. The simulation results and the implementation of each structure are presented. Finally, a comparison between the four proposed structures is done to choose the best proposed structure based on the hardware cost.


INTRODUCTION
Asymmetrical Digital Subscriber Line (ADSL) is very important facility used in many homes and other internet connection centers.It is an application of the digital signal processing techniques which enables home users and consumers to access the high speed applications of internet such as video-on-demand.ADSL provides a downstream capability up to 4 Mbit/s over the existing telephone wires, within a distance up to a few kilometers.Analog signal transmission of ADSL requires high speed and high resolution Analogto-Digital (A/D) converters.A/D converters can be implemented using Σ∆ modulators which allow high sampling rate meanwhile minimize the hardware (Hauser, 1991;Bourdopoulos et al., 2006;Aboushady et al., 2001).High resolution can be achieved through by filtering and decimating a high rate bit stream (Crochirer and Rabiner, 1983;Hongzhi et al., 2006).Recently, single multi rate FIR, single multi rate IIR, decimation filter, three stages comb-FIR-FIR and comb-IIR-FIR are the subjects of many interesting researches (Shahana et al., 2008;Johansson and Wanhammar, 1999;Barrak et al., 2007;Ciric and Radonjic, 2011;Soo-Chang et al., 2012;Dong and Ya, 2011;Tseng and Lee, 2008a, b).In this study, these are the topics which will be used to present four proposed structures.

ADSL STRUCTURE
Figure 1 shows a schematic diagram of the ADSL.Data conversion in ADSL requires 12 bits of resolution at 4 MHz Brambilla and Guidi (2005).The decimation filter highlighted in Fig. 1 is used for reducing the sampling rate from 64 MHz to 4 MHz and also achieving the appropriate resolution which is necessary.The specifications of the decimation filter are shown in Table 1.

SINGLE STAGE ARCHITECTURE OF THE DECIMATION FILTER
A single stage realization of the decimation filter can be done using either a multi rate FIR or IIR filter.

Single stage multi rate FIR decimation filter:
The frequency response and unit step response of the proposed single stage multi rate FIR decimation filter are shown in Fig. 2 and 3, respectively.The order of the proposed FIR filter is 152, so the filter requires many numbers of coefficients (153 coefficients).The implementation of the proposed single stage FIR decimation filter can be done by choosing one of the following methods: • A RAM is used to store the input samples and a ROM is used to store the coefficients.• Reduction in hardware complexity and power consumption can be done using Signed Digit (SD) representation.SD representation of A is as the form of and N are positive integer number.The minimal SD representation uses only two non-zero digits, for example minimal SD representation of 0.484375 is + 2 -1 -2 -6 , so only two right shifts of the input sample and only one "ADD" are required to perform the multiplication.As a result, the implementation of the filter is done using only some shift registers (instead of the RAM and the ROM mentioned in the first method).In fact, minimal SD representation of the coefficients allows that the implementation of the normalized coefficients (|C k | ≤ 1) can be done with only right shifters subsequently wasting area and power is effectively reduced (Brambilla and Guidi, 2005;Abed et al., 2005).
Based on the method 2 and by exploiting the symmetry of filter coefficients, the implementation of the proposed single stage multi rate FIR decimation filter can be done using 307 right shift registers (153 right shift registers are used to store input samples and 154 right shift registers are used for filter coefficients according to the SD representation) (a similar case is shown in Fig. 8).

Single stage multi rate IIR decimation filter:
The frequency response and unit step response of the proposed single stage multi rate IIR decimation filter are shown in Fig. 4 and 5, respectively.The order of the proposed IIR filter is 7 and converting the IIR to nonrecursive form results that the number of the effective normalized coefficients (10 -6 ≤ |c k | ≤ 1) is 205, so the filter really requires a huge number of coefficients to realize.Similar to the FIR decimation filter, the implementation of the proposed single stage IIR decimation filter can be done using a RAM and a ROM or some replaced shift registers when minimal SD representation of the coefficients is applied.In this case similar to the FIR filter presented in previous section, the implementation of the IIR filter can be done using 411 right shift registers.

MULTISTAGE ARCHITECTURE OF THE DECIMATION FILTER
Single stage FIR and IIR implementations of the decimation filter, which were presented in section 3, require so many coefficients that results to occupy a large area of the silicon chip.To solve this problem a multistage architecture is a good solution.It is clear that an anti-aliasing filter is necessary in order to reduce the sampling rate.There are two appropriate multistage architectures that are comb-FIR-FIR and comb-IIR-FIR.The comb-FIR-FIR architecture consists of the following stages: • A pre-filter with the comb behavior and subsequently a frequency response as the form of • A FIR equalizer to compensate the attenuation in the band pass region done by the pre-filter.• A FIR filter as third stage with very steep transition behavior for making a suitable stop-band attenuation.
The comb-IIR-FIR architecture has similar architecture with the exception of the second stage is implemented with one IIR filter.Sampling rate in the input of the two architectures (64 MHz) can be reduced with the factor of 2 n in the first and other stages.This results the factorization of the decimation factor and subsequently reducing the very huge computation tasks.In the proposed decimation filter, the sampling frequencies in the first, the second and the third stage are chosen as 16 MHz, 8 MHz and 4 MHz, respectively.It is clear that sub-sampling factors for the first, the second and the last stage are 4, 2 and 2, respectively.

IMPLEMENTATION OF THE MULTISTAGE DECIMATION FILTER
In this section the implementations of the threestage comb-FIR-FIR and comb-IIR-FIR decimation filters are presented.The block diagram of the filter is shown in Fig. 6 and the implementations of each stage of the proposed filter are separately presented in following three sections.

Implementation of the first stage (comb filter):
The first stage of the proposed decimation filter is a comb filter because this stage of the filter must work at very high sampling frequency Maity and Das (2012).A comb filter of length N is a FIR filter which all its N coefficients are one, so its transfer function is: Eq. ( 1) can be rewritten as: (3) And subsequently: So, the accumulator transfer function can be expressed as: And also the differentiator transfer function is written as: The frequency response of the comb filter is shown in Fig. 7.A single comb filter does not have appropriate ripple in band pass and enough stop band attenuation, so two other stages rare required.Second stage (FIR or IIR equalizer) is required to provide appropriate band pass response and third stage is necessary to provide a good transition response and enough stop band attenuation.

Implementation of the last stage (transition FIR filter):
The last stage of the decimation filter is a FIR filter which is implemented using only shift registers because of using SD representation of the coefficients.This FIR filter improves the transition response of the final decimation filter.The order of this filter is 86, so it can be implemented using 175 right shift registers.It can be seen that the output of the last stage is a data as the form of 12 bits with the sampling rate of 4 MHz while the input of this stage has the sampling rate of 8 MHz.Frequency response of the multistage decimation filter: The frequency responses of the comb-FIR-FIR and comb-IIR-FIR decimation filters are shown in Fig. 9 and 10, respectively.Comparing two three stages filters shows that the hardware of the comb-FIR-FIR is lass than the comb-IIR-FIR hardware.

A COMPARISON BETWEEN FOUR PROPOSED STRUCTURES
Four structures of the digital decimation filter which is used in Σ∆ A/D converters of ADSL were presented in previous sections.Based on the SD representation of the coefficients, a comparison between the four structures is done in Table 2.The comparison shows that the three-stage comb-FIR-FIR decimation filter requires the hardware which is less than the other three structures.

CONCLUSION
In this study, four structures of the digital decimation filter used in Σ∆ A/D converters of ADSL were presented.These four structures were single multi rate FIR, single multi rate IIR, three stages comb-FIR-FIR and comb-IIR-FIR.The hardware minimization was done using the minimal SD representation of the coefficients.The simulation and implementation results were presented.A comparison between the four proposed structures was done to choose the best structure which has the minimal hardware cost.

Fig. 4 :
Fig. 4: Frequency response of the single stage multi rate IIR decimation filter.Magnitude (vertical axis) vs frequency (horizontal axis)

Table 1 :
Decimation filter specifications