An FPGA Implementation of the Natural Logarithm Based on CORDIC Algorithm

: In digital signal and image processing, it’s very common to calculate the value of certain transcendental functions, such as natural logarithmic function. This study introduces the basic principles of the mode of calculation of the hyperbolic systems by using the CORDIC algorithm, then analyses the Field-Programmable Gate Array (FPGA) CORDIC core processing unit in detail. The biggest advantage of the CORDIC algorithm is that its circuit structure is very simple, using only adder and shifter. It is very suitable for FPGA implementation. Based on the iterative algorithm, a FPGA implementation of the natural logarithmic function has been designed. The pipelined-FPGA architecture can achieve a high computational speed, for completing a computation only requires one clock cycle. The relative error values are below 10 -4 , which can satisfy the accuracy requirements.


INTRODUCTION
The natural logarithmic function is widely used in image processing and digital signal processing.For example, to solve some questions in the physical setting of logarithmic imaging processes, Michel and Jean-Charles (1995) used the Logarithmic Image Processing (LIP) model, known to be a compatible mathematical framework.After recalls on the model, that study presents two images transforms: one performs an optimal enhancement and stabilization of the overall dynamic range and the other does of the mean dynamic range.What's more, a new method based on graynatural logarithm ratio bilateral filtering is presented for image smoothing in Guannan Chen's work (Guannan et al., 2008).Therefore, the study of its hardware implementation is necessary.The logarithm is widely implemented with: Table lookup method, Taylor series expansion method and linear approximation method.With the improvement of the accuracy requirements, the table lookup method will consume a lot of resources.Taylor series expansion method will use the multiplier.As precision requirements increase, the demand of the multiplier will become larger.However, the number of multipliers in the FPGA is relatively limited.Linear approximation method can't meet the high precision requirements.
The biggest advantage of the CORDIC algorithm is its circuit structure is very simple, using only adder and shifter.As a hardware efficient algorithm, it is particularly suitable for FPGA implementation.In order to avoid the complexity of the circuit, the idea of the CORDIC algorithm is that decompose the rotation operation into successive basic rotations and every rotation only be realized with add-and-shift operations.

CORDIC ALGORITHM PRINCIPLE
The CORDIC (Coordinate Rotation Digital Computer) algorithm was first introduced by Volder (1959).It is efficient to compute the values of trigonometric functions, such as sin, cos, sinh, cosh, tan.It was later extended to logarithmic, hyperbolic and other functions by Walther (1971).The CORDIC algorithm contains the circumference systems, linear systems, hyperbolic systems, three kinds of rotation system.In a variety of rotation system is divided into the rotation mode and vector mode.To calculate the value of the natural logarithm, it should be the operating mode of the vector model in the hyperbolic system.

Iterative rotations:
The function x 2 -y 2 = 1 is a flat hyperbolic function, its parametric form is (1): (1) And, the matrix equation form is (2): (2) From vector (x 1 , y 1 ) to another vector (x 2 , y 2 ) hyperbolic rotation defined as follows: (3) Its iterative form: The basic idea of the CORDIC algorithm is that not directly use the tanh t operator, but to select a series of special parameter t 1 satisfy tanh t i = 2 -i for hyperbolic rotation.So multiplied by the operator tanh t i becomes multiplied by the operator 2 -i .That is a simple shift operation.Then add direction control factor d i : (5) z i is defined to keep track of the parameter that has been changed: Set the initial vector (x 1 , y 1 ).After N iterations, becomes: Parallel pipelined CORDIC: The CORDIC rotator is normally operated in one of two modes.The first called rotation, rotates the unit vector and then gradually iteration vector endpoints along the hyperbolic convergence on the parameter t ((x, y) = cosh t, sinh t)) point.The second mode called vectoring, rotes the input vector (rcosht, rsinht) to the x axis and gradually converges to (r, 0).Of solving practical problems is performed through cooperation and competition among them.Rotation mode: Vectoring mode: In vectoring mode the rotation produces: When z 1 = 0 , then: If the initial input x 1 = t + 1, y 1 = t -1 satisfy the convergence conditions, the input range is very limited.So how to increase the effective range of the input data is an important problem.The calculation shows that tanh -1 12 = 0.9999999999244972, so [-12, 12] can make the domain of the function close to (-1, 1), the complete domain of the function of x. y 1 /x 1 can also be infinitely close to 1.
By including additional iterations for negative indexes i can increase the data valid input range (Hu et al., 1991) For i>0 When w = -5, it can satisfy the requirements of the input range, so we can start iteration from n = -5, the first formula of iteration ( 13) has been used when n is less than or equal to 0 by, otherwise the second formula of iteration ( 14) has been used.The amount of shift of each level of iteration unit is fixed, when the input data is 16 bits, 22 iterations structure can be used, the sequences of iterative shift are (7, 6, 5, 4, 3, 2, 1, 2 .... 16).And t i is the change parameter for each iterative equation.The floating-point form of t i and its hexadecimal form have been showed in the following Table 1.

FPGA IMPLEMENTATION
Pipelined-CORDIC: In practical applications, the natural logarithmic function calculator should be based on the needs of the target in between running speed and resource consumption.
The pipelined-FPGA architecture can achieve a high computational speed, thereby greatly increasing the efficiency of the system.In this structure, each of the shifter is determined depth.Parameter accumulator's value as a constant direct connection to the accumulator on, do not need storage space and reading time.Figure 1 shows a basic unit in the pipelined structure.The direction control factor d i defines the sign of the adder-subtractors.And t i is the change parameter for each iterative equation.Its value is defined from Table 1.
The inputs and outputs have the same width (16 bits).Extends the bit width can improve the accuracy of the computation.So the data extended to 33, the highest bit is the sign bit.
The end: z = 1/2ln (t).The results of left shift one bit, the interception of the high 16 as a final output.The maximum data bit is the sign bit.For the maximum inputting value 65535, the real result is 11.0903, corresponding to the output of FPGA is FFFF.The remaining output divided by the corresponding value to get the right results.
In this study, the natural logarithmic function calculator is implemented by the FPGA chip-EP2C35F672C8, which costs a total of 4085 logic elements of 33216.The actual f max is 94.18 MHz and satisfy the design requirements.
Function simulation There is a figure of the functional simulation for the calculator.It reflects the logic and timing relationships of the input and output of the calculator.
In the Fig. 2 of this simulation report, clk is a clock signal, xi, yi, zi are the input signal and xo, yo and zo is the output signal.It can be seen from that, the first output data generated after 22 cycles.Then after the rising edge of each clock will generate an output.This reflects the superiority of the pipeline structure of processing speed.randomly selected input values.The relative error values are below 10 -4 , which can satisfy the accuracy requirements.

CONCLUSION
FPGA has a regular internal logic array and connection resources, suitable for digital signal processing tasks.Relative to the general-purpose chip serial arithmetic, FPGA has better parallelism and scalability.CORDIC is generally well-suited for handheld calculators, an application for which cost is much more important than speed.In this study, the CORDIC algorithm principle can be applied to the fast and accurate computation of the natural logarithm, given CORDIC algorithm can be completed by shift and addition operations in the FPGA.The pipelined-FPGA architecture can achieve a high computational speed.The relative error values are below 10 -4 , it satisfies the accuracy requirements.Compared to other hardware realization method, this calculator satisfies the performance requirements in the aspects of operation speed, the calculation accuracy and resource consumption.

Fig
Fig. 1: A basic unit in the pipelined structure

Table 1 :
The floating-point form of t i and its hexadecimal form Table 2 that the natural logarithm calculator has high accuracy for five

Table 2 :
Result analysis