A Great Efficiency Full Adder Cell Based on Carbon Nano-Tube Technology

: In this study, we present a very quick full adder cell that has high energy efficiency based on carbon nano-tube transistor technology This project and other circuits in this study were in different voltages and frequencies with HSPICE software .The results of show that the speed and efficiency of this circuit is obviously better than other circuits like: CMOS and CNFET. Also, this full adder that we present, make great ability to on outlet and it works properly in low voltages


INTRODUCTION
The difficulty of changing measure and physical limitation of silicon transistors , make designers to apply new Nano technology .one of the most hopeful and probable branches of Nano-technology is carbon nano-tube transistor .the usage of COMS transistors cause difficulties like high consumption of electrical current and increase of power consumption ; so, the carbon nano-tube transistors are going to be the alternative of silicon transistors.The general principle of operation and structure of carbon Nano-Tube transistors is similar to current transistors.If you continue using CMOS technology in design of electronic integrated circuits , it causes dimension reduction of COMS transistor based on more law that resulting to improve speed cast and power consumption; but the min aturization of transistors is going to finish , because the circuits are so compressed that the chips will be so hot and the high heat lead to increase the power consumption and decrease of general operation .In recent years, designers have been trying to design circuits based on carbon Nano-Tube transistors (Deng, 2007;Raychowdhury and Roy, 2004).
The summation is one of the main actions in mathematics and it is the base of many other mathematics actions like subtraction, multiplication and address operation.The full adder cell is main pat in complex arithmetic circuits and arithmetic processors and it is an important part of arithmetic and logic unit.The design of an adder with simple structure that has high speed and low power consumption can be very effective for simplifying the arithmetic algorithms and increase of computing system performance (Junming et al., 2001;Zimmermann and Fichtner, 1997;Chang et al., 2003).So, the improve of performance of this circuit will improve the performance of all parts of system (Zimmermann and Fichtner, 1997;Chang et al., 2003).Thereby many designers design different plans with different methods to improve the performance of all parts of system, in recent years.
In this study, we present a full adder cell based on carbon Nano-Tube transistors and then, we compare it with COMS and CNFET adder cell in different situations .Here, we explain about this adder briefly.
COMS adder circuit (Zimmermann and Fichtner, 1997) is made of 28 transistors and designers use COMS technology to make it.Bridge (FA24T) adder cell (Navi and Kavehei, 2008), has 24 transistors and it is design based on low power structure and high efficiency and fully symmetrical bridge.Adder circuits Hybrid-1 (Chang et al., 2003), Hybrid-2 (Goel et al., 2006) are designed based on low power XOR/XNOR Circuit and respectively has 26 and 24 transistors.TG (Transmission Gate) FA cell (Weste and Eshraghian, 1993) has 18 transistors and it is designed based on transfer Function theory and XOR Gate.and CNFETbased FA cells including the CNT-FA-1 based on minority function with 8 transistors and 7 capacitors (Navi et al., 2009), CNT-FA-2 is based on majority-not, NAND and NOR functions which is composed of 12 transistors and 8 capacitors (Navi et al., 2010a) and the CNT-FA-3 based on minority function and utilizes 5 capacitors and 8 transistors (Navi et al., 2010b).

CARBON NANOTUBE TRANSISTOR
The basic idea of this carbon nano-tube was discovered by Igima on 44, by chance (Ijiima, 1991).It is a layer of granite that it is twisted and ruled with special angle.(Carbon nano-tube has interesting and special and rare characteristic but the characteristics which make this new arrangement of carbon atom to an important material in micro Electronic are: • Transfering of Electrons Ballestic in length of tube. • The carbon nano-tube can be conductor and semiconductor by changing the angle of twisting on graphit layer.Carbon nano-tube characterize by chiral vector (C h ) and C h calculated by nexus (Deng, 2007): 1 ����⃗ and  1 ����⃗ are unit vectors of an organized network of carbon atoms and (n 1 , n 2 ) are Integers that show the of a point and a paper and they define the caberality of tube and characterize the nano-tube .(The length of C h tube calculates by ( 2) formula (Deng, 2007) : The diameter of CNT calculates by ( 3) formula and usually it is about a few nano-meters: The relation of eve voltage to geometric shape of nano-tube to achievement of different eve voltages is based on nano-tube diameter eve in CNTFET and it is marked by (4) formula: The carbon nano-tube divide to different group based on n 1 and n 2 integers.(If n 1 = n 2 we call the carbon nano-tube, Armichair.(If n 1 = 0 and n2 = 0, we call it zigzag and in other situations we call it chiral (Raychowdhury and Roy, 2004;Bok Kim et al., 2009).
The first nano-tube transistor with SWNT , metal contact and golden or platinum source Drin made by tans, Dekker and Verschueren in 443 (Tans et al., 1998).
A carbon nano-tube transistor is similar to a MASOFT and it includes 3 parts: source, Drin and gate.It means the basic operation of field effect nano-tube transistors is similar to current silicon transistors (Deng, 2007).In which, we consider a nano-tube as a channel and put an Also, such channel should be controlled by gate electrode.These transistors turn off/on by gate, electro statically (Chen, 2004).We introduce 3 different type of carbon NLT here, in brief: • Schottky barrier CNFET (SB-CNFET): IT works based on Schottky barrier.In this kind of transistor the touch points of Drin and source joins directly to the channel of nano-tube.The length and width of Schottky barrier and so the conduction of it characterize by gate voltage electrostatically.Two important factors or these kind of transistors are, at first, the energy of barrier in Schottky barrier has limitation on CNTFEL conduction in on mood.Second, these kind of transistors present the characteristic of strong that limit the use of these transistors in circuits with the current logic of CMOS.

• MOSFET-like CNFETs (MOS-CNFETs):
There is impurity through the carbon nano-tube (This impurity is strongly similar to current MOSFET.(These transistors have unipolar behavior.these kinds of transistors because of their physical similarities to silicon technology, the Si-MOS circuits with MOS-CNFETs circuits.

• Band-to-band tunneling CNFET (T-CNFET):
This kind of transistor shows the strong am bipolar characteristics and it applies for design of low power consumption because of it cuts the #cut off $ current very well (Raychowdhury and Roy, 2007;Paul et al., 2006 ) .

PROPOSED FULL ADDER CELL
The main idea of this design is taken from TGA FA cell in Weste and Eshraghian (1993).The recommended adder designed based on transferring function adder designed based on transferring function and XOR gate.This circuit showed in Fig. 1.The out lets of recommended circuit build in 3 stages.In X knot and first stage, we build A B ⊕ and in Y knot we build A □ B and at last in other stages we build SUM and C out outlets.The Sum and C out functions in this adder calculate based on ( 5) and ( 6) formula.
When we replaced a gate with two CNFET transistors, it does not need to con duct CR in R signal and the number of up adder transistors is be creased.we consider the diameter of transferring gate of replacing nano-tube transistors, so large that the eve voltage of through fare is nearly zero and so, we don't experience the voltage drop in circuit outlet and the knots of outlet in this circuit are in complete sway that this factor give a high assurance to the circuit and it cases reduction in leakage wasting power.
We use from a newer design of XOR to perform this circuit and we use is instead of XOR in this circuit.The first model of recommended adder cell (Fig. 3) We replaced transferring gate with current transistors and also, we used from a better structure of XOR function and finally, the increase of nano-tube diameter make it better than the former circuits in COMS technology all of above help us to achieve carbon nanotube technology The results are, reduction in area of circuit, decrease of delay and therefore increase of The arc with largest average power and send data to that selected node in a unicast manner.

SIMULATION AND COMPARING
Because ALL of the adder cells and the final model of proposed adder are simulated by HPSPICE software.To evaluate the proposed deigns, we simulated them using Synopsys HSPICE.32nm CMOS technology has been used to simulate CMOS circuits and compact SPICE model which is proposed in Deng (2007) has been used to simulate CNFET-based circuits.This standard model has been used for unipolar MOSFETlike CNFET devices.The goal of this simulation is to increase the efficiency of all circuits by use of the minimal dimension for transistors.We perform all simulation on the same terms and room temperature.The operating frequencies are 250 MHz and 500 MHz.And power supplies were used 0.5 V and 0.65 V.The proposed designs optimized were for speed and power at 0.65 V and 250 MHZ.
Then we kept the circuit parameters constant and the simulation did in other terms.
To calculate the delay we have tested all possible input transitions (56 patterns) and then the delay has been measured for each transition.The maximum delay has been reported as the delay of each FA cell.
The average power consumption include: dynamic power consumption, short circuit, static and it measured by simulator.Because we want to make compromise between power and delay and also to general assessment of circuits efficiency, we calculated the multiply of Power in Delay (PDP).
Previous CNFET-based FA cells have more power consumption than CMOS FA cells but in our design reduced power consumption significantly.The PDP of the first proposed design is 96.4, 95.84, 94.64, 93.13, 95.11% and 91.38% better than CCMOS, Hybrid1, TG, CNT-FA-1, CNT-FA-2 and CNT-FA-3 respectively.The second design consumes less power and is more high-performance compared to the first proposed design.Finally, the results indicate that the third proposed cell consumes less power and has the best delay and PDP in comparison with the other cells mentioned in Table 1.
According to the Table 1, the delay and efficiency of proposed circuits better than the other adder circuits.The proposed circuit in all different voltages has the least delay and the best efficiency.As a result the proposed FA cells have the best PDP in different conditions.
Figure 4 shows PDP diagrams at 250 MHz and 500 MHz frequencies.It can be concluded from the charts that the PDP of the proposed designs are less than the previous designs.
Figure 5 shows the waveforms of the proposed design at 0.5 v supply voltage.This design performs very well at low supply voltages and high frequencies and has full swing outputs.

CONCLUSION
This study has proposed a novel high-speed and low-voltage CNFET-based Full Adder circuit based on carbon Nano-tube technology and transfer gate to achieve the least delay and the most efficiency .We did the simulation of above full adder cell in different term and compare it with silicon and carbon nano-tube technology of full adder circuits is better than other that circuits in delay and efficiency.The suitable capability in outlets and low power consumption in comparison of former CNFET adder circuits are the advantages of this circuit.All knots of this circuit are in complete sway voltage that it gives the circuit a high assurance.

Fig. 1 :Fig. 2 :
Fig. 1: The first draft of recommended full adder B A

Fig. 4 :
Fig. 4: PDP of the designs at different test conditions

Table 1 :
Simulation results for the FA cells AT 0.65V and 0.5V supply voltage efficiency Moreover, the let out signals in this circuit have complete sway and they performed just with 14 transistors.