Designs and Implementations of Low-Leakage Digital Standard Cells Based on Gate-Length Biasing

: In this study, a minimum set of low-power digital standard cells for low-leakage applications are developed and introduced into SMIC (Semiconductor Manufacturing International Corporation) 130 nm CMOS libraries, which include basic logic gates such as inverter, NAND, NOR, XOR, XNOR and flip-flop. The inverter, NAND, NOR and flip-flop standard cells based on the gate-length biasing technique are proposed to achieve low Energy Delay Product (EDP). The XOR and XNOR standard cells are optimized based on transistor-level. All circuits are simulated with HSPICE at a SMIC 130nm CMOS technology by a 1.2V supply voltage. The proposed several standard cells attain large leakage reductions. A mode-10 counter is verified with the proposed standard cells by using commercial EDA tools. The leakage and total dynamic power dissipations of the mode-10 counter using the proposed standard cells provide a reduction of 21.27 and 3.06%, respectively. The results indicate the proposed standard cells are a good choose in low leakage applications.


INTRODUCTION
Technology scaling increases the density and performance of integrated circuits, resulting in large power dissipations.With the growing uses of portable and wireless electronic systems, energy-efficient designs have become more and more important in VLSI chips (Agarwal et al., 2004).The total energy consumption in a CMOS circuit includes mostly two components: switching energy due to charging and discharging for loads and static energy dissipation that is caused by leakage currents of MOS devices.Before the CMOS process is scaled into deep sub-micro process, dynamic energy loss has always dominated power consumption, while leakage dissipation is little.The aggressive scaling of device dimensions and threshold voltage has significantly increased leakage current exponentially, which attracts extensive attentions.
There are several leakage sources in nanometer CMOS processes: sub-threshold leakage current, gate leakage current and band-to-band tunneling leakage current.In three leakage sources, the sub-threshold leakage is the dominant contributor to total leakage at 130 nm and is forecast to remain so in the future, because it increases exponentially with threshold voltage (V th ) (Fallah and Pedram, 2005).Many leakage reduction techniques have been proposed recently at various design levels, such as MTCMOS (Multi-Threshold CMOS) power-gating technique (Kao and Chandrakasan, 2001), DTCMOS (Dual Threshold CMOS) (Zhang et al., 2011), VTCMOS (Variable Threshold CMOS) (Peiravi and Assai, 2008) and GLB (Gate-Length Biasing) (Gupta et al., 2006) have been proposed in recent years and achieved considerable energy savings.
Low power, high speed and small area are three main objectives in IC design.Today's advanced designs require a careful balancing of many competing challenges.PDP (Energy Delay Product) metric provides a good compromise between speed and delay, which is written as: Cell-based design flow has been widely used for digital chip designs with commercial EDA tools.In order to realize a low-power chip, standard cell libraries and IP (Intellectual Property) cores should be constructed with low-power design techniques.Many power reduction techniques have been proposed for standard cell libraries.Semicustom design methodologies were proposed with MTCMOS powergating standard cells (Kim and Shin, 2007.The authors presented low-leakage standard cell based ASIC design methodologies for both static CMOS and domino logic (Jayakumar and Khatri, 2007).The transistor-level DTCMOS was also used for low-leakage standard cells (Nagarajan et al., 2009).
For a typical technology with a sub-threshold slope of 100mV/decade, each 100mv reduction in V th will cause an order of magnitude increase in leakage currents (Wang et al., 2006).In short channel devices, with increasing of the gate length, the threshold voltage increases, so that the leakage decreases exponentially and delay increases linearly.The Gate-Length Biasing (GLB) technology increases the channel length of transistors to alter the threshold voltage and reduces leakage exponentially in both active and standby modes, while delay increases only linearly with the increasing of the gate length (Hu and Wang, 2011).It is reported that small biases in channel length of transistor can afford significant leakage savings with small performance impact (Heo and Shin, 2007).
In this study, a minimum set of low-leakage digital standard cells are developed, which include basic logic gates such as inverter, NAND, NOR, XOR, XNOR and low-leakage power flip-flop.These standard cells are optimized to achieve low Energy Delay Product (EDP).The layout design, abstract and standard-cell characters of these standard cells are also described.In order to show energy efficiency of the proposed standard cells, a mode-10 counter is verified with the proposed standard cells by using commercial EDA tools.The results indicate the proposed standard cells are a good choose in low power design.

Basic logic gate cells with gate-length biasing:
The basic gates such as inverter, NAND and NOR are important elements in digital circuits, since they are largely used.However, basic logic gate standard cells used in most current CMOS processes such as SMIC 130 nm are mostly based on standard CMOS logic.We increase the gate-length of basic logic gates including inverter, NAND and NOR from 130 nm to 250 nm by 10 nm step.HSPICE simulations are carried out for the basic standard cells with Gate-Length Biasing technology.The leakage dissipation and delay of the inverter are shown in Fig. 1.With increasing of the gate length, the leakage power decreases exponentially and delay increases linearly.Therefore, it is possible that the best EDP is achieved by using channel length biasing technology.The EDP of the inverter, NAND and NOR cells are shown in Fig. 2. The results show that the basic standard cells with the GLB technology have lower EDP than the SMIC one with the standard gate-length.The inverter, NAND and NOR cells have the best EDP when their gate length is 0.18, 0.19 and 0.20 um, respectively.The inverter cell provides an EDP reduction of 23.7%, thought its delay is slightly larger than the SMIC one.

Low power XOR and NXOR circuits:
In commercial standard-cell library such as the SMIC, the XOR circuit is typically realized based on a TG logic structure with 12 transistors, as shown in Fig. 3a.The XOR and XNOR structures with 10 transistors used in this study are shown in Fig. 3b (Wang and Hu, 2011).Because of   their simple structures, it is expected that they have lower power than the SMIC 130nm one.
The energy delay product of the two XOR cells is shown in Table 1.The results show that the XOR has lower EDP than the SMIC one.The XOR has 53% energy saves and provides an EDP reduction of 34%, although its delay is slightly larger than the SMIC one.The power dissipations of the proposed flip-flop cell have been comprised with the other two ones, as shown in Fig. 5.

Low
Figure 5 show that the low-leakage flip-flop cell with GLB has lower energy consumption than the SMIC one.Compared with the SMIC standard cell, the lowleakage flip-flop cell has 19% energy saves.
The leakage dissipations of the three flip-flop standard cells are shown in Table 2. TGMS-GLB attains a power reducing of 19% compared with the DFFQX1.

LAYOUT DESIGNING AND POST-LAYOUT SIMULATIONS
Basic logic gate cells using GLB: The layout of the proposed basic logic gate standard cells is shown in Fig. 6, which include inverter, neither NAND, NOR, XOR and XNOR with GLB.The metal lines are placed horizontally at the top and the bottom for the power supply (VDD) and ground (VSS).All of the layout heights of the standard cells are 3.69um that is the same as 130nm SMIC ones.
The leakage power dissipations of the two inverter standard cells are shown in Table 3 by  The leakage power of NAND and NOR standard cells are shown in Table 4.In Table 4, Compared with the 130nm SMIC standard cells, the leakage power of the proposed NAND and NOR cells with the GLB technology are reduced greatly.
The EDP of the SIMC and proposed XOR cells is compared in Table 5 by using post-layout simulations.The results show that the proposed XOR cell is better optimized than the SMIC one.The leakage power dissipations of the SIMC and proposed XOR cell are shown in Table 6.The leakage of the proposed XOR standard cell is lower than SMIC one expect for the state of AB = "11".

STANDARD CELL DESIGNS
In this section, the design flow of the standard cells is presented.Taken an example, the standard-cell generation for the low-leakage flip-flop with GLB (TGMS-GLB) is presented in detail.The standard-cell design flow is shown in Fig. 10.The GDS database is generated by using the stream out function of IC5141.Then, the auto place and route (P&R) library is created using this GDS database.The layouts of the standard cells are verified by using the Calibre tool and spice netlists are generated from their layouts.The synthesis library is generated by using the liberty NCX and HSPICE.
After the layout design, the abstract view should be created in Library Exchange Format (LEF) for standard From the LEF file, we can see that all the all Pins are abstracted.In the LEF file, the size of the flip-flop cell is defined as 6.9 µm×3.69 µm.To perform characterization, Liberty NCX is used to run circuit simulations for the library cells to determine the cell behavior.It writes out a description of the cell characteristics in the Liberty format (.lib).The library can then be used for timing, power and noise analysis with various tools such as Design Compile and Prime Time.In addition, Liberty NCX can convert existing libraries from one format to another.For a characterization task, the template file must specify the SPICE model file name, the SPICE net list directory and the SPICE simulator executable, as shown in Fig. 12.The input and output library names should be also specified.
After the characterization, we can get a library in the liberty format (.lib) that can be used for timing and power analysis with various tools such as Design Compile.We can use the Library Compile tool from Synopsys capture this liberty (.lib) file and translates them into Synopsys internal database (.db) format for synthesis.

MODE-10 COUNTER USING THE PROPOSED STANDARD CELLS
In order to estimate power information, a mode-10 counter is synthesized by using Design Compile. Figure 13 and 14 show the two synthesis results by using the SMIC 130 nm standard cells and the proposed standard cells, respectively.
As shown in Fig. 13 and 14, the area of the two results is the same and the leakage power and the total dynamic power of the mode-10 counter using the proposed standard cells provide a reduction of 21.27 and 3.06%, respectively.Although the dynamic power dissipation of the proposed standard cells only has a little reduction, they can achieve large total power savings because of their low leakages.

CONCLUSION
Technology scaling increases the density and performance of integrated circuits, resulting in large power dissipations.Cell-based design flow has been widely used for digital chip designs with commercial EDA tools.In order to realize a low-power chip, lowpower standard cell libraries are important.
In this study , a minimum set of low-power standard cells have been developed, which include basic logic gates such as inverter, NAND, NOR, XOR, XNOR and flip-flop.The proposed inverter, NAND, NOR and flipflop standard cells are optimized to achieve low energy delay product (EDP) by using the gate-length biasing technique.The proposed XOR and XNOR standard cells are optimized based on transistor-level.The proposed several standard cells attain large leakage reductions.A mode-10 counter is verified with the proposed standard cells by using commercial EDA tools.The leakage and total dynamic power dissipations of the mode-10 counter using the proposed standard cells provide a reduction of 21.27 and 3.06%, respectively.The results indicate the proposed standard cells are a good choose in low power design.

Fig. 1 :
Fig. 1: Leakage power dissipation and delay of the inverter standard cell

Fig. 4 :
Fig. 4: Flip-flop standard cell based on Transmission Gate Master-Slave Structure with Gate-Length Biasing (TGMS-GLB) -leakage flip-flop with gate-length biasing: A flip-flop is important element in digital circuits.The C 2 MOS flip-flop (DFFQX1) is used in the SMIC 130 nm standard-cell library.A low-leakage power flip-flop standard cell based on Transmission Gate Master-Slave structure (TGMS) with GLB technology is used to achieve low energy delay product in this study, as shown in Fig. 4 (Hu and Wang, 2011).The gate-length in the TGMS flip-flop is increased to 140nm (TGMS-GLB).HSPICE simulations been carried out for the three flip-flops cells (DFFQX1, TGMS and TGMS-GLB).
using post-layout simulations.The inverter cell with GLB technology (INVX1_R) has a leakage reduction of 41.61%, compared with SMIC one (INVX1_SMIC13).

Fig. 6 :
Fig. 6: The layouts of the proposed basic logic gate standard cells for SMIC 130 nm

Fig. 10 :
Fig. 10: Design flow of the standard cells

Fig. 13 :
Fig. 13: Design compile synthesis results of the mode-10 counter using the SMIC 130nm standard cells

Table 1 :
EDP comparisons of two XOR standard-cells

Table 2 :
Leakage power of three flip-flop cells (nW)

Table 3 :
Leakage power of inverter standard cell using post-layout

Table 4 :
NOR2X1_R are the proposed NAND and NOR cells with the GLB technology, respectively.
Leakage power of NAND and NOR standard cells using post-layout simulations (pW)