A Comparative Study on SOI MOSFETs for Low Power Applications

Silicon on Insulator (SOI) technology has become one of the most promising technologies in semiconductor fabrication industry for its numerous advantages. This study presents merits and demerits of different SOIs presented in literatures and a comparative study is done based on several design and performance issues for low power applications. From the study it is found that Fully Depleted SOI MOSFET (FDSOI) technology is preferred due to its thin size, reduced leakage current and improved power consumption characteristics etc. compared to those of PDSOI and bulk silicon technology.


INTRODUCTION
Rapid growth in semiconductor technology urges the industrial playmaker to compete against them. Moore's Law indicated that the number of transistors on an integrated circuit chip doubles every one and a half years (Moore, 1998;Mack, 2011;Mack, 2003;Bondyopadhyay, 1998;Akter et al., 2008a;Mohd-Yasin et al., 2004;and Reaz et al., 2007). The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is playing a vital role in technology advancement for the past 2 decades (Reaz et al., 2003). MOSFETs offer advantages in performance gain and cost reduction especially in low power application in comparison to others (Tuomi, 2002).
The Fig. 1 shows the cross sectional view of a typical MOSFET which exhibit bilateral symmetry i.e., the channel carriers can be made to flow in either direction, depending on bias polarity. This symmetry is important in certain MOSFET applications. The 2 channel terminals have been named according to which one supply the carriers to the channel and which receives carrier from it and these 2 terms are source and drain, respectively.
In this study, design and performance comparisons are presented among different architectures of SOI, MOSFETs illustrated in the literatures for last 2 decades. From the study it is clear that every PDSOI, MOSFET, FDSOI and MOSFET structural designs have their own advantages and disadvantages and are preferred for particular applications.

SOI MOSFET TECHNOLOGY
Silicon on Insulator (SOI) technology has become one of the most promising technologies in semiconductor fabrication industry. The SOI transistor has been introduced by Mueller andRobinson in 1964 (Mueller andRobinson, 1964;Colinge, 1987;Pelella and Fossum, 2002). The Silicon on Insulator features (SOI) technology features a low capacitance which enables high speed operation. That is, the supply voltage can be lowered to cut the power consumption while adequate speed is provided. However, the advantages of SOI technology are not limited to the area of speed and power, it also has advantages in term of the ability to withstand high temperature and handle high voltage. A thin layer about tens of nanometer active silicon is placed on top of a thick layer of insulator such as silicon dioxide (SiO 2 ) or sometimes referred as Buried Oxide (BOX) (Sugii et al., 2008;Colinge, 2008;Kilchytska et al., 2011;Kranti et al., 2010) and this dielectric isolation of silicon reduces the parasitic or internal junction capacitance on components and thus improves device performance by a huge percentage (Lee et al., 1998;Saha, 2009;Saha, 2008). Figure 2 and 3 shows the comparison between the Bulk CMOS and SOI CMOS in term of leakage current path and it is clear that the leakage current flows in bulk CMOS substrate whereas in SOI CMOS there is no leakage current flow in the substrate.
There are two types of SOI MOSFETs, depending on the operating mode; they are Partially Depleted SOI MOSFET (PDSOI) and Fully Depleted SOI MOSFET (FDSOI). Figure 4 shows the PDSOI configuration where an undepleted neutral region at the bottom of the SOI layer exits. The maximum depletion width is lesser than the thickness of SOI layer. It has an advantage over bulk MOSFET, that there is no leakage current and no latch-up problem (Reaz et al., 2006). Chen et al. (2008) proposed the design of a 65nM Partially Depleted Floating Body SOI MOSFET for off state leakage current depending on modeling of parasitic current through the floating body effect (Chen et al., 2008). For low power applications or high performance technology, the supply voltage is chosen as low as feasible to minimize the power consumption and threshold voltage is also reduced as much as possible. This research shows the parasitic current through the floating body heavily influences the off state leakage current (Ioff) for non zero drain voltage (Vds). On the other hand, in case of FDSOI the entire region of SOI layer is fully depleted which offers additional advantages such as low threshold voltage, small leakage current, smaller floating body effects. Because of these characteristics, FDSOI is most appropriate device to give the better performance at low supply voltage for power consumption to be reduced. Figure 5 shows the cross section of the FDSOI MOSFET, where the maximum depletion width is greater than the thickness of the SOI layer (Warner and Grung, 1999). Zhang and Roy (2002) introduced the Double Gate Fully Depleted SOI MOSFET (DGFD SOI) for low and high power applications (Zhang and Roy, 2002). The coupling between the front gate and back gate has been also investigated to study about the implications of the noise immunity and circuit reliability. The Fig. 6 shows the cross section of the DGFD SOI MOSFET with front gate and back gate tied together. Wei et al. (1998) proposed the design and optimization of DGFD SOI MOSFET for low voltage low power circuit (Wei et al., 1998). The comparison has been made between the DGFD SOI MOSFET and conventional Single Gate FD SOI MOSFET (SGFD) in term of the circuit delay, power dissipation and power delay. The results shows that the DGFD SOI MOSFET can improve the circuit performance and benefit the supply voltages scaling and the threshold voltage of DGFD SOI MOSFET can be controlled dynamically. Besides, the minimum channel length of DGFD SOI MOSFET can be reduced by 30% in comparison to that of SGFD SOI MOSFET. Thus, the DGFD SOI MOSFET is appropriate candidate for deep submicron low voltage and low power circuit.

SOIs FOR LOW POWER APPLICATION
The design of SOI MOSFET for low power applications is proposed by Assaderaghi et al. (1997) where dynamic voltage threshold control is possible and is suitable for ultra low voltage (0.6V and below) operation (Assaderaghi et al., 1997). It is important for the design to have a low leakage current of the transistor at the zero gate voltage. A Dynamic    Lee et al. (1998) Threshold Voltage MOSFET (DTMOS) can be made by performing a connection tie on both the gate and the body of SOI MOSFET together. The research shown that a single MOSFET can have a higher threshold voltage when the voltage at gate to source equal to zero hence the produce a reduction in leakage current and higher speed operation. The DTMOS MOSFET configuration can be shown in Fig. 7 and 8. Lee et al. (1998) also proposed a new design with an auxiliary MOSFET in which gate and drain are shorted to the main transistor's gate and thus source is connected to the channel body of the main transistor ( Fig. 9) (Lee et al., 1998). The result has shown a low threshold voltage, high operation voltage and high drain current as compared to conventional MOSFET and previous DTMOS designs.
Better performance achieved as it improved sub threshold voltage by 11% and increased drain current capability by 46% and decreased the leakage current and a comparison is given in Table 1.
Body effect of the Tri-Gate Bulk for DTMOS is presented by Han et al. (2006). In this study it is proposed that the back gate (bulk substrate) is to be utilized to offer the dynamic threshold voltage operation that exhibits high VT at VG = 0V to and low VT at VG = VDD = 0.6V to achieve low power and high performance.
The SOI MOSFET technology is also widely used in wireless and Radio Frequency (RF) applications where most of the electronic equipments can be assumed as 'power hungry' devices (Marufuzzaman et al., 2010;Akter et al., 2008b) because people love to perform many applications at the same time and therefore, power consumption rate is usually high. At this level, SOI technology plays a main role and yet reliable to be utilized in low power applications. The RF and mainboard circuit power consumption is to be reduced and at the same time the performance of the devices needs to be maintained under lowest bias possibility condition. Deen et al. (2005) have carried out a research on RF function in low power low voltage applications and achieved a better performance compared to previous studies done by Wong and Luong (2002), Tarim and Ismail (1999) and Seng et al. (1998). The results are tabulated in Table 2.
Moreover thermal conductivity of the SOI MOSFET is considered as one of the crucial parameters which cannot be neglected (Hailong and Kursun, 2010). The use of Buried Oxide (BOX) with poor thermal conductivity causes the devices to experience a huge temperature rise which can be higher than 80º Celsius (Colinge, 2004). As a result, the device characteristics shift and cause malfunction condition. A tiny cutoff frequency could be sufficient for specific applications while maintaining the minimum power consumption and maximized the battery lifetime. It is shown that the improved design enhance power consumption and lifetime of the devices (Emam et al., 2010;Emam et al., 2008).
Therefore, Partially Depleted SOI MOSFET (PDSOI) usually used in high performance microprocessors, analog and RF systems and also memory applications. By making a connection tie on both the gate and the body together, a SOI MOSFET can have a higher threshold voltage when the voltage at gate to source equal to zero hence produce a reduction in leakage current and higher speed operation. However, PDSOI usually face a main drawback which is its physical limitation due to packaging scalability and the heat behavior also needs to be considered (Chen et al., 2008).
Fully Depleted SOI MOSFET, however, built up with the ultra thin film (5 to 20nm) of Silicon. Nowadays, FDSOI technology is preferred due to its thin size, reduced leakage current and improved power consumption characteristics etc. compared to those of PDSOI and bulk silicon technology. However, the main drawback of FDSOI is its complex fabrication process (Vitale et al., 2010).

CONCLUSION
It has been shown that the appropriate candidate for low power application is Fully Depleted SOI MOSFET due to a great advantages in term of low Researchers Seng et al. (1998) Tarim leakage current and power consumption is drastically reduced. Also there is no floating body effect and hence it is easier to control the short channel effects. The main challenge for FDSOI MOSFET compared to PDSOI MOSFET is the new methodology are excessively needed for defect detection in very thin layer whichever a very thin body can brought a huge challenge to manufacture and to implement the performance boosters.