Design of an Inductor-less Lna Using Resistive Feedback Topology for Uwb Applications

Low Noise Amplifier (LNA) is one of the essential components in Ultra Wideband (UWB) devices. Conventional LNA suffers from large chip area, high power consumption and inadequate Noise Figure (NF). A compact UWB LNA in the bandwidth of 3.1 to 10.6 GHz is proposed. The design is based on inductor-less configuration using the resistive shunt feedback topology and noise canceling techniques for wideband and high gain characteristics. Designed in 0.18-µm CMOS technology without applying any inductors and capacitors in the core circuit, the chip area is only 0.001 mm 2 and consumes 16.11 mW of power at 1.5-V supply. The maximum gain is 18.01 dB and the minimum NF noise is 1.324 dB.

The UWB LNA needs to provide a good input matching over the bandwidth of 500 MHz and sufficient gain to amplify the weak signal at the receiver as well as to overcome the noise effects from subsequent stages.On top of that, the NF of the UWB LNA must be minimized as low as possible since it plays a main role in defining the receiver's sensitivity.Moreover, the size of LNA needs to be physically small in order to provide power efficient and reduce the fabrication cost respectively.
Significant research and various approaches have been proposed to design UWB LNA.There are several techniques that commonly used to achieve wideband input matching for UWB LNA such as the inductive peaking, the Distributed Amplifier (DA), the filter type amplifiers, the common gate amplifier and the resistive shunt feedback amplifier (Chen et al., 2011).However, these techniques may suffer from several disadvantages which include large chip area, high power consumption and inadequate NF (Nilsaz et al., 2010;Hsu et al., 2010).
This study presents the design of an UWB LNA that aims to achieve low power, small size and medium gain (Power gain >10 dB).The gain enhanced resistive shunt feedback based on noise canceling techniques is used in designing inductor less UWB LNA as it is able to accomplish wideband input matching, relative low NF, sufficient voltage gain and high linearity.Furthermore, this technique is widely used to release the tradeoff in the UWB LNA.

CONVENTIONAL ARCHITECTURE
Resistive feedback topology: Basically, feedback is a common technique that is applied in the design of wideband amplifiers to obtain the input matching.In the resistive feedback, LNA can achieve very wideband (from 0-22 GHz) and also it has low power consumption and high gain.This technique takes into the consideration since negative feedback had a tendency to minimize the input impedance of amplifier as well as extend its bandwidth with reduction of tradeoff gain.As compared to the other techniques, a smaller chip area can be achieved by resistive feedback LNAs configuration since there are no or less inductors being introduced and utilized.To enhance the performance of LNAs in terms of bandwidth extension and input matching, numerous techniques were proposed and developed based on the resistive feedback approach.
The basic schematic of the common source amplifier with a resistive feedback is shown in the Fig. 1 (Chang and Hsu, 2010).However, this Common Source (CS) amplifier is incapable to achieve a good input matching and low NF.In regards to this limitation, the voltage buffer has been introduced and used with feedback resistor in order to improve input matching and NF.This modified design schematic is shown in Fig. 2.
In this topology, theoretically the increasing of the transistor transconductance g m is resulting to the reduction of the NF.By appropriate designing of a feedback resistor R f and load resistor R L respectively, the input matching can be enhanced.Voltage buffer implementation via a source follower is widely used as indicated in Fig. 3 (Chang and Hsu, 2010).

Noise cancelling technique:
The noise cancelling concept is to generate the noises with the opposite phase polarities in different path and cancel the noises at the output.Since, the cancelation is not relevant to the input impedance, this technique allows for simultaneously noise cancellation and impedance matching.Figure 4 shows a simplified resistive shunt feedback LNA by using noise canceling technique.This LNA composed of a transistor M 1 , a resistor R F and feed forward voltage amplifier with a gain of A X (A X >0).To have maximum power transfer, the input impedance Z in is designed to match to source impedance, Rs.

METHODOLOGY
The proposed UWB LNA consists of a noise cancelling and an output buffer stages using resistive feedback topology as shown in Fig. 5. R S is 50Ω source impedance which connects the input pad via a capacitor C in .In the noise cancelling stage, R F1 is a shunt feedback resistor which purposely used for Fig. 4: Simplified resistive shunt feedback using noise cancellation technique Fig. 5: Proposes resistive shunt feedback noise cancelling UWB LNA wideband matching as well as for sensing the signal and noise of the input transistors M 1 , M 2 and M 3 respectively to combine the signal and subtract the noise of M 1 .R D1 and R D2 are being used as the load resistors.To subtract the noise at the drain of M 2 , the polarities of the signal at the drains of M 1 and M 2 will be in-phase.If A 2 is implemented in a common source configuration, the signals at the drains of M 1 and M 2 will be out of phase.Therefore, a subsequent stage is needed to convert the polarities.In this way, the linearity will be decreased and power consumption increases.Hence, the common gate configuration has been adopted in this UWB LNA design rather than a common source.
The input impedance Z in is equal to the parallel combination of the input parasitic capacitance C A and resistance R in .C A is the gate to source capacitance of M 1 , M 2 and R in is [RF1 + (1/gm 3 )] / [1 + (gm 1 /gm 3 )] at low frequency, the input matching is achieved by setting R in to 50Ω.As the frequency increases, Z in will deviate from 50Ω because the admittance of C A increases as well.Therefore, to keep C A as small as possible is important for wideband input matching.By adding M 3 , the part of the current of M 3 flows into M 1 which increases gm 1 .As a result, for a given gm 1 , the required size of M 1 is small which reduces C A and maintains a wideband input matching.
In order to achieve wideband output matching, the source follower is commonly incorporated in UWB amplifier.However, for low voltage applications, R out is designed to be 50Ω.It not only provides 50Ω wideband output matching, but also increases the overall gain.The design parameters are summarized in a Table 1.

RESULTS AND DISCUSSION
The circuit simulations of the proposed CMOS UWB LNA design are performed in Mentor Graphics environment based on CEDEC 0.18 um CMOS process   6 shows that the voltage gain increases with the increment of supply voltage but utilization of high supply voltage will increase the power consumption of the device.Table 2 represents the relationship of the supply voltage and power consumption that has been simulated.
Load capacitor has been introduced to the circuit at the output stage which purposely to perform correlation analysis and effects to the voltage gain.As shown Fig. 9, degradation of the gain was observed with increment of load capacitor.Selected value of load capacitor is 50, 100, 150 and 200 fF, respectively.
Based on this study, resistive shunt feedback incorporated in noise cancelling technique is able to  3 shows comparative performance summary of the proposed design with the other reported UWB LNAs.The layout of the proposed UWB LNA drawn in Mentor Graphics 0.18 um CMOS process technology is shown in Fig. 10 environment based on CEDEC.The core area is only 0.032 × 0.032 mm 2 (0.0010 mm 2 ).

CONCLUSION
Inductor-less UWB LNA in 0.18-um CMOS technology with core area of only 0.001 mm 2 is proposed in this study.Based on inductor-less design configurations, the resistive shunt feedback and noise canceling techniques were employed.The amplifier was operated at frequency band 3.1 to 10.6 GHz with maximum gain of 18.01 dB and minimum NF of 1.324 dB.

Fig. 6 :
Fig. 6: Simulation results of voltage gain versus frequency with difference supply voltage Figure

Fig. 8 :
Fig. 8: The input and output noise of UWB LNA

Fig. 10 :
Fig. 10: Layout of the proposed UWB LNA layout achieve a better performance in term of voltage gain, noise Fig., low power consumption and extend the bandwidth as well as small chip area.Unfortunately, the performance was degraded when the LNA was operated in the high frequency band; this is due to the effect of parasitic capacitances.Table3shows comparative performance summary of the proposed design with the other reported UWB LNAs.The layout of the proposed UWB LNA drawn in Mentor Graphics 0.18 um CMOS process technology is shown in Fig.10environment based on CEDEC.The core area is only 0.032 × 0.032 mm 2 (0.0010 mm 2 ).

Table 1 :
UWB LNA design parameters

Table 2 :
Gain (dB) and power consumption (mW) when applying difference supply voltage