VLSI Architecture Using a Modified SQRT Carry Select Adder in Image Compression

Designing a compressor with the parameters such as power, delay and area are most considerable metric in VLSI design. Compression process plays a vital role in image processing and the main building block is the multiplier. Image conversion is done in MATLAB and the compression is done using VHDL in VLSI. Finally, the compression ratio is predicted using MATLAB. CPA (Carry Propagation Adder) and CSA (Carry Save Adder) occupies more chip area than other adders. To overwhelm the problem this study proposes a modified Square Root Carry Select Adder (SQRT CSLA) in Dadda multiplier used in compression system. The modified SQRT CSLA performs faster than other adders and power consumption is low. Compression techniques pay more attention in image processing. In this study 4-2 compressor is employed to reduce the complexity.


INTRODUCTION
In recent communication technology Very Large Scale Integration (VLSI) circuits in low power becomes very important to design a high performance and convenient devices.The parameters such as speed, cost and area become most important parameters in VLSI.These parameters play a vital role in performance.More focus is given for consumption of low power to achieve high speed in low cost to occupy small area.Day by day the importance of low power VLSI is increasing because of its performance.In image processing it finds a strong application hence the VLSI tool is not a general purpose tool for systems.Imaging and video applications becomes fastest growing sector in day today life.It finds more application in medical science, machine vision, digital cameras, HDTV, security surveillance and set top box.Most powerful technique is image compression in image processing.The adder used in the compressor is to reduce the storage space required and to increase the data bit transfer rate.Preserving the image quality by increasing the reliability is preferred.It also find its application in nanoscale technology because of its higher speed it has become more important.
Multiplication is the fundamental for all mathematical operations and finds its application in computation system and graphics in digital computer and in signal processing systems.Apart from addition and subtraction, more processing time and hardware resources are required for it.In VLSI technologies, there is a need to develop the chip design tools for continuous development.An algorithm was proposed (Pekmestzi, 1999) based on a different mechanism which consists of one bit of the multiplier and one bit of the multiplicand and both can be interchanged.The operand is used as a bit in each step.The multiplier circuit design is more complex since it consists of number of transistors and gates in CMOS VLSI technology.
The compression of fractal image weaknesses was analyzed.The rate-distortion performance was encoded and decoding speed by considering cluster centres using Mean Shape-Gain Vector Quantization (MSGVQ) code book method (Raouf and Dietmar, 2000).This method is not competitive with the state-of-the-art wavelet coders and does not generate an embedded code because it allows scalability and progressive transmission.
A low power multiplier by booth algorithm (Chen et al., 2003) was designed to reduce the implementation complexity.The proposed column based, row based and hybrid based multipliers can design dynamic-range determination units.But reduction in switching activity is difficult.A new methodology was proposed with XOR and exclusive NOR for 4-2, 5-2 compressor (Chip-Hong et al., 2004) consumes low power and acquires sufficient drivability on CMOS technology at very low voltages.The 4-2 compressors display better efficient power and 5-2 compressor composed to carry generator module.Its operation is reflected in a tree structured multiplier.
Two methods in lossy compression technique (Wei et al., 2006) were developed using JPEG 2000 for efficient entropy encoding and rate control.The specified bit rate distortion is minimized by rate control method for the specified bit rate.The authors proposed a Greedy Heap based Rate-Control algorithm (GHRaC), by implementing a greedy marginal analysis method to achieve efficient post compression rate control using the heap sort algorithm and for entropy coding an Integrated Rate-control and Entropy-Coding (IREC) algorithm reduces the complexity of computation.An automatically-determined Region of Interest (ROI) (Chen and Chih-Chang, 2007) scheme embedded in JPEG 2000 in video compression employed with Lagrangian multiplier to optimize ROI masks in order to reduce distortion.Locating ROI in an image with no obvious object or with complex background becomes semi-automatic.
In this study a new technique is discussed to reduce delay and low power consumption for image compression in which an image is converted to hexadecimal from decimal using MATLAB.The compression is carried out in VLSI in which the 4-2 compression unit consists of a modified SQRT Carry Select Adder (CSLA).The modified SQRT CSLA (Square Root Carry Select Adder) adder uses 16 bit.

PROPOSED METHODOLOGY
An image is randomly selected in which the image is compressed, to be compressed the process is carried out in two steps.The first step consists of a converting the pixel values in the image to the hexadecimal values, which is executed in MATLAB.The second step is to compress the hexadecimal values using 4-2 compressor technique in VHDL.The third step is to calculate the compression ratio.The block diagram for the proposed study is given in Fig. 1.
Image: A RGB image of 8 bit is selected and it is converted into gray scale.RGB stands for red, green Hexadecimal: Hexadecimal is one of the numeral system.It uses the standard decimal from 0 to 9 and for 10 to 15 it takes English alphabet from A to F or a to f.A nibble is said to have one hexadecimal digit.00 to FF represents two hexadecimal values.Since it is user friendly it finds more application in computer by programmers, system designers and digital electronics.Initially the uncompressed image of larger quantity in decimal is converted to hexadecimal which is executed in MATLAB.For image compression using VLSI design the 4-2 compressor receives hexadecimal as input for further process in order to transfer or store the image data efficiently.
Compressor: A 3-2 compressor (Siliveru and Bharathi, 2013) is used in multiplier which has 3 inputs with 2 outputs (Fig. 2).A 3-2 static mirror compressor is employed to connect slow input with fastest output (Hsu et al., 2006).In this study a 4-2 compressor is utilized which compresses four partial products.The 4-2 compressor (Momeni et al., 2015) consists of series connected of two full adders which is designed with XOR, XNOR gates and Multiplexers.In the proposed separately which consumes more power, high more space.AOI in this modified SQRT CSLA is to calculate final sum and output carry becomes more efficient.
Binary to Excess-1 Converter consists of many full adders and half adders.The modified CSLA using BEC use AOI instead of either full adder or half adder which reduces area, power consumption and speed up the operation in A multiplexer also known as data selector has a select line to carry analog or digital signals.A ne carries one signal.For 2:1 multiplexer 1 select line is needed.Multiplexer reduces integrated circuit package number in turn reduces the cost.

SIMULATION RESULTS
Figure 4 is taken as input for the system.
The Dadda multiplier designed using modified SQRT CSLA has been developed using VHDL and synthesized in Xilinx ISE14.2. Figure 5 -2 compressor.Comparing the delay attained by Array, Booth, Vedic multipliers (Sumit and Deepak, 2010) with proposed Dadda multiplier during compression of a Table 1.The delay attained by proposed Dadda multiplier is 18.641 nsec  Table 2 shows the design and features of multipliers in each group shown in Fig. 2.
The reduction in circuitry for delay improvement is shown in Table 3.  4.
The simulation result of a compressed image is shown in Fig. 6 and the delay occurred by the proposed method seems to be better when compared with other multipliers (Sumit and Deepak, 2010).

Output image:
The output image obtained is 5.34 KB (5478 bytes) is shown in Fig. 7.The compressed ratio is 66.80%.

CONCLUSION
An image is randomly selected to be compressed in two steps to calculate delay time.The first step is to convert the pixel values in the image to the hexadecimal values, which is executed in MATLAB.The second step is to compress the hexadecimal values in VHDL.In this proposed method image compression is performed by 4-2 compressor technique using modified SQRT CSLA.The delay metric is measured and compared with other multipliers and the simulation result shows the measured performance metric is more efficient than the compared existing multipliers.

Fig. 6 :
Fig. 6: Simulation result of compressed image in model SIM