A Comparitive Study of Vedic BCD Multiplier using Reversible Logic Gates

Hardware implementation for decimal operations are more important rather which is more useful in the field of technical (DSP, Microprocessor, Digital Image Processing, etc.) and non-Technical (banking calculation, currency conversion, even in office ledgers, etc.). The main purpose of this research is to improve the speed of the digital processors such as adders, multipliers, which are the prime factors in digital circuits. Here is the architecture of a BCD multiplier, which can increase the efficiency and performance of the digital systems. The binary and decimal numbers are converted to BCD ad then multiplied using Vedic algorithm. High speed multiplier architecture that we designed here is using Vedic mathematics. Urdhva-Tiryagbyham sutra is used to design Vedic multiplier. Power and area are the other paramount of the VLSI design, to diminish that here reversible logic gates are used. The circuit in this study is constructed using Vedic Multiplier with reversible logic gates. Verilog HDL code has been written to perform the simulation. The area and power consumption of Vedic multiplier and Vedic multiplier using reversible logic are calculated using cadence software and both of the results are compared. Vedic multiplier is used in DSP applications such as IIR and FIR filters, FFT and convolution.


INTRODUCTION
Multiplication is the most common and important arithmetic operation which has wide applications in different areas of science and technology.The rudimentary block of Digital Signal Processing is the Multiplier (Mehta et al., 2013;Sriraman and Prabakar, 2012).Multiplication is used in many applications such as instrumentation and measurement, animations, graphics, communication and audio and video processing, etc.
Three different styles (Anitha et al., 2012;Anitha and Bagyaveereswaran, 2013) are there to do the multiplication in decimal (Premananda et al., 2013).First way is directly multiply the two decimal numbers.Second way is to change the decimal number into the Binary form and then perform the multiplication; solution will be again converting to decimal.Third way is each and every digit will be converted into binary and multiplied; the final product will arrive from partial product generated by binary multiplication.Third way of decimal multiplication is adopted in this study.There are two challenges in designing BCD multiplier (Vaibhav et al., 2014).First one is the multiplication process and the second one is the binary to BCD converter.So we are designing a high speed modified Vedic BCD multiplier using the reversible logic (Sriraman and Prabakar, 2012) which has been implemented in this thesis, which is faster than the conventional BCD Multiplier and produces less power consumption (Subudhi et al., 2014).We can implement the FIR Filter as which is the important feature of DSP (Krishnaveni and Umarani, 2012).

MATERIALS AND METHODS
Vedic mathematics: Vedic mathematics (Subudhi et al. 2014;Pradhan and Panda 2014) are an ancient mathematics which is more efficient than other mathematic techniques.Vedic mathematics is used in many applications such as arithmetic operations, theory of numbers, compound multiplications, squaring, cubing, square root and cube root etc. Totally there are 16 sutras and 14 sub-sutras in Vedic mathematics.Among those sutras, only 3 sutras and 2 sub-sutras are used for multiplication.Urdhva-Triyagbhayam is an universally adopted method for all multiplication.So this method is chosen to design Vedic multiplier.This method is also called as vertical-cross method.The following steps are used in Urdhva-Triyagbhayam multiplication method (Mehta et al., 2013): Step 1: The Least significant bit will be first multiplied and the corresponding product will be assigned as direct product.
Step 2: Next highest bit will cross multiplied with the LSB and the product will be added together.If carry occurs that will be carried out to the next step.
Step 3: Again the next bits will be multiplied in cross and vertically and then availed products will added along with the carry occurred in the last step.Repeat for other higher bits.
Step 4: Partial products are added together with the carry if generated.
The following is an example of Urdhva-Triyagbhayam method:

Implementation of 4×4 vedic multiplier:
The following method is 4-bit binary multiplication using Urdhva-Triyagbhyam technique.First the decimal value is converted into binary and then the binary multiplication is done using Urdhva-Triyagbhyam method.
Figure 1 is the block diagram of 4×4 Vedic multiplier.It consists of half adders and full adders (Vaibhav et al., 2014).

BINARY TO BCD CONVERTER
Shift-add 3-algorithm is used to perform binary to BCD conversion.This concept can be used on a binary number with any number of bits.For a four bit number, four shifts must be performed.If the number is greater  than four, each shift is performed and then it must be added to three.The final BCD number will be in the uppermost bits of the new number, once all four bits have been shifted (Table 1).

Implementation of 4 bit Vedic multiplier using reversible logic:
Reversible logic: Most of the Low power designs are now-a-days designed using Reversible Logic gates Assarian et al. (2012) because which has no internal power.
It's a one to one mapping between the vectors of inputs vs outputs as shown the example Fig. 2.
By the Pigeonhole principle the reversible logic gates will have same number of inputs and outputs.using one not gate and identity gate one input bit can be there which can have two possible reversible gates.The reversible computation can be carried out in a reversible manner, where there won't be a power dissipation.There are 2 states to perform this: • Logically reversible-means that unique retrievable of inputs and outputs.
The block diagram and the equivalent quantum diagram is given in Fig. 3a and 3b respectively.
Tofolli gate: Its otherwise called as "controlledcontrolled-not", which as 3 inputs and 3 outputs.The first two bits are set and the third bit will do the inversion, otherwise all the input bits will be same (Fig. 4).Using Feynman gate we can calculate the sum of the half adder and using the Tofolli gate we can calculate the carry of the half adder by making it's third  The multiplication of filter co delayed signal is performed by using vedic multiplier.By using vedic multiplier the speed of the process increased.The future work may be we can implement The multiplication of filter co-efficients and delayed signal is performed by using vedic multiplier.By using vedic multiplier the speed of the process increased.The future work may be we can implement the FIR filter using this technique Singh et al., 2014).

RESULTS
The Verilog code for vedic 4 Fig. 1 is simulated in Modelsim 6.5 as well as in xilinx and the results are given below in (Fig. 8) (Binu Siva vedic 4-bit multiplier in Modelsim 6.5 as well as in xilinx in Fig. 9. Simulation

CONCLUSION
In this study, we have implemented 4 multiplier using reversible logic.The Binary to BCD converter is design and synythesized and the multiplication unit has been implemented.The vedic multiplier is implemented in conventional method and the proposed design i.e., vedic multiplier block is modified using reversible logic gates.So that the comutation time is reduced so far.Quantum cost of the system is reduced further.The number combinational cells have been diminished when compare to the normal conventional binary multiplication.The comparison of vedic multiplier and vedic multiplier using reversible logic is given in Fig. 2 From the results, We can show that vedic multiplier using reversible logic is more efficient and faster than the normal vedic multiplier.The area and power consumption of vedic multiplier is considerably reduced when reversible logic is applied (Table 2).
Using the reversible vedic multiplier logic we can implement the FIR/IIR filters, Convolution and deconvolution, etc. which are all the essential block in the DSP Processor.

Fig. 1 :
Fig. 1: Block diagram of 4×4 vedic multiplier It can be described by mapping the inputs a, b and c to the outputs a, b and c XOR (a and b) (Kumar Chunduri et al., 2013).It's a main application of quantum error correction: Inputs are A, B and Gate is another important gate which has a low quantum cost as compared to other gates.A single Peres gate can work as half adder when the third input C = 0. Let be the input and output vector of a 3*3 Peres gate, where Input = (A, B, C) and Output = (P = A, Q = A⊕B, R = AB⊕ C) (Husain et al., 2013) (Fig. 5).DKG gate: Let be the input and output vector of a 4*4 Peres gate, where Input = (A, B, C) and Output = (P = B, Q = A'C ⊕ AD', R = (A⊕B) (C⊕D) ⊕ CD, S = B ⊕ C ⊕ D).A single DKG gate can work as full adder when the first input A= 0 (Kumar Chunduri et al., 2013; Devendra and Vidhi, 2012) (Fig. 6).

bit
Vedic multiplier, Fig. 10.Simulation bit Binary to BCD converter and Fig. 11.bit Vedic multiplier using Reversible logics which is show in the Fig. 3 to 7 is implemented and the results are shown below: = 1100 Output: P = 01100000 and the RTL schematic also shown in the Fig. 12. 4-bit bit reversible vedic using Cadence.Figure 2 showing the synthesized report of Vedic multiplier Vs CONCLUSION have implemented 4-bit vedic multiplier using reversible logic.The Binary to BCD converter is design and synythesized and the multiplication unit has been implemented.The vedic multiplier is implemented in conventional method and , vedic multiplier block is modified using reversible logic gates.So that the so far.Quantum cost of the .The number combinational cells have been diminished when compare to the normal bit vedic multiplier with that of 4-bit vedic multiplier using reversible logic gates Vedic multiplier using reversible logic gates (4-bit) 13873.078nw 105

Table 1 :
Binary to BCD conversion

Table 2 :
Comparison of 4-bit vedic multiplier multiplier using reversible logic gates