Abstract

The Reconfigurable FIR filters are commonly used digital filters which find its major applications in digital signal processing and multi-standard wireless communications. The Direct form of FIR filter used in DSP application which consumes more area and power. To overcome this problem Multiplier Control Signal Decision (MCSD) window schemes is incorporated into direct form FIR filter in order to dynamically change the filter order. Conventional reconfigurable FIR filter is designed using Russian Peasant Multiplier which consumes more area and delay due to poor performance of adder used in multiplication unit. In this study, modified reconfigurable FIR filter is designed to further reduce the area, power and time. In proposed Reconfigurable FIR filter, a Wallace adder is replaced by carry select adder with sklansky adder in Russian Peasant Multiplication technique. Hence, modified Reconfigurable FIR filter with carry select adder with sklansky adder consumes less area, delay and power than the conventional Reconfigurable FIR architecture with Russian Peasant Multiplication technique.

Keywords:

Carry save adder, FPGA, MCSD scheme, modified reconfigurable FIR filter, Russian peasant multiplier, sklansky adder,

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Competing interests

The authors have no competing interests.

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The authors have no competing interests.