Abstract

This study presents an architectural approach to the design of Low power and area efficient reconfigurable Finite Impulse Response (FIR) filter. FIR digital filters are used in DSP by the virtue of its, linear phase, fewer finite precision error, stability and efficient implementation. The proposed architectures implemented by using carry save adder, it offer Low power and area reductions and compared to the best existing reconfigurable FIR filter implementations in the literature and the proposed architectures have been implemented and tested on Spartan-3 xc3s200-5pq208 Field-Programmable Gate Array (FPGA) and synthesized.

Keywords:

Channelizer, CSA, FIR filter, high speed filter, reconfigurability,

References

1. Alaoui, C., 2011. Design and simulation of a modified architecture of carry save adder. Int. J. Eng., 5(1): 102-113.
   
2. Alex, S. and J. Selvakumar, 2013. FPGA implementation of novel reconfigurable pipelined architectures for low complexity FIR filters. Int. J. Appl. Res. Stud., 2(3).
   
3. Anandan, K. and N.S. Yogaananth, 2014. VLSI implementation of reconfigurable low power FIR filter architecture. Int. J. Innov. Res. Comput. Commun. Eng., 2(1).
   
4. Chaplot, R. and A. Paliwal, 2014. Low power and high speed reconfigurable FIR filter based on a novel window technique for system on chip. Int. J. Digit. Appl. Contemp. Res., 2(6).
   
5. Geethalakshmi, M. and A. Jayamathi, 2013. Reduction of multiplier in FIR filter using common sub expression elimination algorithm. Int. J. Eng. Sci. Innov. Technol., 2(3), ISSN: 2319-5967.
   
6. Jijina, G.O. and V. Ranganathan, 2014. Low power architecture for reconfigurable fir filter for SDR. World Appl. Sci. J., 32(2): 164-168.
   
7. Kishore, S.R.C. and K.V.R. Rao, 2012. Implementation of carry save adder in FPGA. Int. J. Eng. Adv. Technol., 1(6), ISSN: 2249-8958.
   
8. Lee, S.J., J.W. Choi, S.W. Kim and J. Park, 2011. A reconfigurable FIR filter architecture to trade off filter performance for dynamic power consumption. IEEE T. VLSI Syst., 19(12): 2221-2228.
   CrossRef    
9. Mahesh, R. and A.P. Vinod, 2008. Coefficient decimation approach for realizing reconfigurable finite impulse response filters. Proceeding of IEEE International Symposium on Circuits System, pp: 81-84.
   CrossRef    
10. Mahesh, R. and A.P. Vinod, 2010. New reconfigurable architectures for implementing FIR filters with low complexity. IEEE T. Comput. Aid. D., 29(2): 275-288.
    CrossRef    
11. Mitola, J., 2000. Software Radio Architecture: Object-oriented Approaches to Wireless Systems Engineering. John Wiley and Sons, Chichester, New York.
    CrossRef    PMCid:PMC111545    
12. Park, J. and K. Roy, 2008. A low complexity reconfigurable DCT architecture to trade off image quality for power consumption. J. Signal Process. Syst., 53(3): 399-410.
    CrossRef    
13. Peiro, M.M., E.I. Boemo and L. Wanhammar, 2002. Design of high-speed multiplier less filters using a no recursive signed common sub expression algorithm. IEEE T. Circuits-II, 49(3): 196-203.
    
14. Ramkumar, B., H.M. Kittur and P.M. Kannan, 2010. ASIC implementation of modified faster carry save adder. Eur. J. Sci. Res., 42(1): 53-58.
    
15. Samueli, H., 1989. An improved search algorithm for the design of multiplier less FIR filter with powers-of-two coefficients. IEEE T. Circuits Syst., 36(7): 1044-1047.
    CrossRef    

Competing interests

The authors have no competing interests.

Open Access Policy

This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Copyright

The authors have no competing interests.