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Abstract
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Article Information:
Thermal Aware Floor planning Technique for Nano Circuits
G. Nallathambi, D. Gracia Nirmala Rani and S. Rajaram
Corresponding Author: G. Nallathambi
Submitted: July 24, 2014
Accepted: September 13, 2014
Published: September 15, 2014 |
Abstract:
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The strongest challenge that a VLSI designer has to face today is the extremely high heat generation within a chip which not only degrades the performance but also the yield and reliability are greatly affected. The situation even became worse with the more number of wires in a single chip and due to path to path temperature variations within the chip. Nowadays VLSI circuits have immense variations in temperature and their linear relationship between metal resistance and temperature causes distinct delay through wires of the same length. The aim of this study is to analyze floor planning algorithms and wire plan methods to reduce the temperature dependent delay in global wires. We propose a temperature dependent wire delay estimation method for thermal aware floor planning algorithms, which takes into account the thermal effect on wire delay. The experiment results show that a shorter delay can be achieved, the congestion and reliability issues as they are closely related to routing and temperature using the proposed method.
Key words: Congestion, floor planning, thermal, wire delay, , ,
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Cite this Reference:
G. Nallathambi, D. Gracia Nirmala Rani and S. Rajaram, . Thermal Aware Floor planning Technique for Nano Circuits. Research Journal of Applied Sciences, Engineering and Technology, (10): 1279-1284.
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ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
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