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Abstract
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Article Information:
Design of a Novel Optimized MAC Unit using Modified Fault Tolerant Vedic Multiplier
R. Deepa and A. Shanmugam
Corresponding Author: R. Deepa
Submitted: June 20, 2014
Accepted: July 19, 2014
Published: August 20, 2014 |
Abstract:
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In this study, the design of optimized Multiplication and Accumulation (MAC) unit with modified Vedic multiplier is presented. To design a MAC unit, efficient multiplier is used to increase speed and to reduce area and power. Conventional MAC is designed using without fault tolerant Vedic multiplier. But it consumes more area and power. And also less delay. So MAC unit is changed to design the efficient Vedic multiplier. Conventional MAC unit with regular Vedic multiplier is not working for some of the inputs condition. To overcome this fault, novel Vedic multiplier is proposed and designed using less half adder and Full Adder. Simulation is carried out using Modelsim 6.3c. Synthesis and Implementation is carried out using Xilinx and FPGA Spartan 3.
Key words: Fault tolerant multiplier, FPGA spartan 3, MAC, vedic multiplier, , ,
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Cite this Reference:
R. Deepa and A. Shanmugam, . Design of a Novel Optimized MAC Unit using Modified Fault Tolerant Vedic Multiplier. Research Journal of Applied Sciences, Engineering and Technology, (7): 900-906.
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ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
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