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Abstract
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Article Information:
Fault Tolerant Design for Magnetic Memories
Arun Kumar P., P. Pandian and J. Raja Paul Perinbam
Corresponding Author: P. Arun Kumar
Submitted: August 01, 2013
Accepted: August 21, 2013
Published: March 29, 2014 |
Abstract:
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This study presents a Fault Tolerant memory cores based on the property of Component Reusability, a method for Fault Tolerance for content addressable memories. The memories used in the design are 256, 512, 1024 and 2048 bytes. The fault is injected into the circuitry operation by using Automatic Test Pattern Generators (ATPGs). The design has been implemented in Cadence 90 nm technology and tested with Fault Injection Circuits and ATPG effectiveness was found out to be 100% at a frequency of 500 MHZ.
Key words: ATPG, BIST, fault tolerant, LFSR, magnetic memories, ,
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Abstract
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Cite this Reference:
Arun Kumar P., P. Pandian and J. Raja Paul Perinbam, . Fault Tolerant Design for Magnetic Memories. Research Journal of Applied Sciences, Engineering and Technology, (12): 2491-2495.
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ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
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