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2013 (Vol. 6, Issue: 19)
Article Information:

The Design and Simulation of Embedded FIR Filter based on FPGA and DSP Builder

Zhao Zeng-Rong
Corresponding Author:  Zhao Zeng-Rong 

Key words:  DSP builder, embedded FIR filter, FPGA QuartusⅡ , , , ,
Vol. 6 , (19): 3489-3494
Submitted Accepted Published
August 09, 2012 September 17, 2012 October 20, 2013

The aim of this study is to introduce a new way to design an embedded FIR Filter whose parameters can be adjusted easily to meet different need. FIR Filter plays an important role in the digital signal processing which can implement the function such as low pass filter, pass band selection and etc. A 37 steps low pass FIR filter is designed and simulated in DSP Builder and MATLAB by Filter IP Core which can be converted into VHDL file to be used in QuartusⅡ and FPGA device as a embedded model quickly and easily. The simulation result shows the FIR Filter meets the requirement of parameters.
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  Cite this Reference:
Zhao Zeng-Rong, 2013. The Design and Simulation of Embedded FIR Filter based on FPGA and DSP Builder.  Research Journal of Applied Sciences, Engineering and Technology, 6(19): 3489-3494.
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ISSN (Online):  2040-7467
ISSN (Print):   2040-7459
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