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2013 (Vol. 5, Issue: 08)
Article Information:

A Low Power Op Amp for 3-Bit Digital to Analog Converter in 0.18 m CMOS Process

Noor A.B.A. Taib, Md. Mamun, Labonnah F. Rahman and F.H. Hashim
Corresponding Author:  Labonnah F. Rahman 

Key words:  CMOS, DAC, op-amp, weighted resistor, , ,
Vol. 5 , (08): 2592-2598
Submitted Accepted Published
August 09, 2012 September 03, 2012 March 15, 2013
Abstract:

Digital to (DAC) is used to get analog voltage corresponding to input digital data in VLSI circuit design with greater integration levels. However, providing linear current and voltage outputs with the use of strictly CMOS devices presents the need for a low power operational amplifier (op-amp) circuit. In this research, the analysis of op-amp circuit for 3-bit DAC is illustrated. In order to reduce the power dissipation, weighted resistor is utilized in the proposed design. To design the op-amp circuit for 3-bit DAC, the design has been implemented in CEDEC 0.18 m CMOS process. The simulated result shows that, under 8 V as the supply voltage the total power dissipation for the proposed DAC is 43.6 nW. Moreover, 143.17 m is found as the total chip area of the designed op-amp circuit for 3-bit DAC.
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  Cite this Reference:
Noor A.B.A. Taib, Md. Mamun, Labonnah F. Rahman and F.H. Hashim, 2013. A Low Power Op Amp for 3-Bit Digital to Analog Converter in 0.18 m CMOS Process.  Research Journal of Applied Sciences, Engineering and Technology, 5(08): 2592-2598.
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ISSN (Online):  2040-7467
ISSN (Print):   2040-7459
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