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2012 (Vol. 4, Issue: 14)
Article Information:

Design and Implementation of Hardware Based Entropy Analysis

S. Saravanan, K. Chakrapani and R. Silambamuthan
Corresponding Author:  S. Saravanan 

Key words:  Donít care bits, entropy analysis, test data compression, zero and one filling techniques, , ,
Vol. 4 , (14): 2082-2086
Submitted Accepted Published
April 04, 2012 April 25, 2012 July 15, 2012

The aim of this study is hardware implementation of the Entropy analysis. Designing and verifying entropy analysis is the major finding of this study aper. Entropy tells how much amount of data can be compressed. Entropy analysis plays a major role in scan based SoC testing. Size and complexity have been the major issues for current scenario of System-on-a-Chip (SoC) testing. Test data compression is a must for such cases. Entropy analysis is taken for both specified and unspecified bits (donít care bits). Unspecified bits are specified using Zero and One fill algorithms. The X-filling technique is applied for fixed to fixed codes. The proposed method is successfully tested on ISCAS89 benchmark circuits.
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  Cite this Reference:
S. Saravanan, K. Chakrapani and R. Silambamuthan, 2012. Design and Implementation of Hardware Based Entropy Analysis.  Research Journal of Applied Sciences, Engineering and Technology, 4(14): 2082-2086.
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ISSN (Online):  2040-7467
ISSN (Print):   2040-7459
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